From b866bd132f3ddd99c36d0499dda888c7980f43dc Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Sun, 31 Mar 2019 18:23:49 -0700 Subject: [PATCH] Correcting read/write port assignments --- TLB/src/TLB.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py index adf6b971..aaa55da2 100644 --- a/TLB/src/TLB.py +++ b/TLB/src/TLB.py @@ -55,8 +55,8 @@ class TLB(): # Add submodules # Submodules for L1 Cache m.d.submodules.cam_L1 = self.cam_L1 - m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port - m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.read_port + m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port() + m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port() # Permission Validator Submodule m.d.submodules.perm_valididator = self.perm_validator -- 2.30.2