From b89086efd386cc0b4eb4fcbd5f097d359dcac5a3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Oct 2019 03:38:58 +0000 Subject: [PATCH] back.rtlil: it is not necessary to match binop operand width. --- nmigen/back/rtlil.py | 1 - 1 file changed, 1 deletion(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index e7ec34c..298d2f9 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -490,7 +490,6 @@ class _RHSValueCompiler(_ValueCompiler): rhs_wire = self(rhs) else: lhs_sign = rhs_sign = True - lhs_bits = rhs_bits = max(lhs_bits, rhs_bits) lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign) rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign) res_bits, res_sign = value.shape() -- 2.30.2