From b8a61edc2fc361a77dc932dc9ca3f6633ec354d9 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 3 Jun 2019 02:22:55 +0000 Subject: [PATCH] hdl.dsl: allow adding submodules with computed name, like with domains. --- nmigen/hdl/dsl.py | 3 +++ nmigen/test/test_hdl_dsl.py | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 03e7e23..30629c4 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -83,6 +83,9 @@ class _ModuleBuilderSubmodules: def __setattr__(self, name, submodule): self._builder._add_submodule(submodule, name) + def __setitem__(self, name, value): + return self.__setattr__(name, value) + class _ModuleBuilderDomainSet: def __init__(self, builder): diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 2677582..0e703e0 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -505,6 +505,12 @@ class DSLTestCase(FHDLTestCase): m1.submodules.foo = m2 self.assertEqual(m1._submodules, [(m2, "foo")]) + def test_submodule_named_index(self): + m1 = Module() + m2 = Module() + m1.submodules["foo"] = m2 + self.assertEqual(m1._submodules, [(m2, "foo")]) + def test_submodule_wrong(self): m = Module() with self.assertRaises(TypeError, -- 2.30.2