From b8d39c3d5295e7fdeb0e769c2bd84fe929457ef0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Mar 2019 02:50:36 +0000 Subject: [PATCH] add MID testing --- src/add/nmigen_add_experiment.py | 37 +++++++++++++++++--------------- src/add/test_add.py | 2 +- src/add/unit_test_single.py | 23 ++++++++++++++------ 3 files changed, 37 insertions(+), 25 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index b7d58ddf..a77868c6 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -175,14 +175,14 @@ class FPID: def __init__(self, id_wid): self.id_wid = id_wid if self.id_wid: - self.in_mid = Signal(width, reset_less) - self.out_mid = Signal(width, reset_less) + self.in_mid = Signal(id_wid, reset_less=True) + self.out_mid = Signal(id_wid, reset_less=True) else: self.in_mid = None self.out_mid = None def idsync(self, m): - if self.id_wid: + if self.id_wid is not None: m.d.sync += self.out_mid.eq(self.in_mid) @@ -207,7 +207,7 @@ class FPAddSpecialCases(FPState, FPID): m.d.comb += self.mod.in_b.copy(in_b) #m.d.comb += self.out_z.v.eq(self.mod.out_z.v) m.d.comb += self.out_do_z.eq(self.mod.out_do_z) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -264,7 +264,7 @@ class FPAddDeNorm(FPState, FPID): m.submodules.denormalise = self.mod m.d.comb += self.mod.in_a.copy(in_a) m.d.comb += self.mod.in_b.copy(in_b) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -336,7 +336,7 @@ class FPAddAlignMulti(FPState, FPID): #m.d.comb += self.out_a.copy(self.mod.out_a) #m.d.comb += self.out_b.copy(self.mod.out_b) m.d.comb += self.exp_eq.eq(self.mod.exp_eq) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -436,7 +436,7 @@ class FPAddAlignSingle(FPState, FPID): m.submodules.align = self.mod m.d.comb += self.mod.in_a.copy(in_a) m.d.comb += self.mod.in_b.copy(in_b) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -514,7 +514,7 @@ class FPAddStage0(FPState, FPID): m.submodules.add0 = self.mod m.d.comb += self.mod.in_a.copy(in_a) m.d.comb += self.mod.in_b.copy(in_b) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -587,7 +587,7 @@ class FPAddStage1(FPState, FPID): m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -802,7 +802,7 @@ class FPNorm1(FPState, FPID): m.d.comb += self.stb.eq(norm_stb) m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -856,7 +856,7 @@ class FPRound(FPState, FPID): m.d.comb += self.mod.in_z.copy(in_z) m.d.comb += self.mod.in_roundz.eq(roundz) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -894,7 +894,7 @@ class FPCorrections(FPState, FPID): """ m.submodules.corrections = self.mod m.d.comb += self.mod.in_z.copy(in_z) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -932,7 +932,7 @@ class FPPack(FPState, FPID): """ m.submodules.pack = self.mod m.d.comb += self.mod.in_z.copy(in_z) - if self.in_mid: + if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): @@ -951,12 +951,12 @@ class FPPutZ(FPState): self.out_mid = out_mid def action(self, m): + if self.in_mid is not None: + m.d.sync += self.out_mid.eq(self.in_mid) m.d.sync += [ self.out_z.v.eq(self.in_z.v) ] with m.If(self.out_z.stb & self.out_z.ack): - if self.in_mid: - m.d.sync += self.out_mid.eq(self.in_mid) m.d.sync += self.out_z.stb.eq(0) m.next = "get_a" with m.Else(): @@ -1051,8 +1051,11 @@ class FPADD(FPID): if __name__ == "__main__": - alu = FPADD(width=32, single_cycle=True) - main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports()) + alu = FPADD(width=32, in_wid=5, single_cycle=True) + main(alu, ports=alu.in_a.ports() + \ + alu.in_b.ports() + \ + alu.out_z.ports() + \ + [alu.in_mid, alu.out_mid]) # works... but don't use, just do "python fname.py convert -t v" diff --git a/src/add/test_add.py b/src/add/test_add.py index dece8961..d63c26f1 100644 --- a/src/add/test_add.py +++ b/src/add/test_add.py @@ -73,6 +73,6 @@ def testbench(dut): yield from run_edge_cases(dut, count, add) if __name__ == '__main__': - dut = FPADD(width=32, single_cycle=True) + dut = FPADD(width=32, id_wid=5, single_cycle=True) run_simulation(dut, testbench(dut), vcd_name="test_add.vcd") diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py index 3dba32ee..640aeb53 100644 --- a/src/add/unit_test_single.py +++ b/src/add/unit_test_single.py @@ -36,7 +36,8 @@ def match(x, y): (x == y) ) -def get_case(dut, a, b): +def get_case(dut, a, b, mid): + yield dut.in_mid.eq(mid) yield dut.in_a.v.eq(a) yield dut.in_a.stb.eq(1) yield @@ -63,15 +64,19 @@ def get_case(dut, a, b): yield continue out_z = yield dut.out_z.v + out_mid = yield dut.out_mid yield dut.out_z.ack.eq(0) yield break - return out_z + return out_z, out_mid -def check_case(dut, a, b, z): - out_z = yield from get_case(dut, a, b) +def check_case(dut, a, b, z, mid=None): + if mid is None: + mid = randint(0, 6) + out_z, out_mid = yield from get_case(dut, a, b, mid) assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z) + assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid) def run_test(dut, stimulus_a, stimulus_b, op): @@ -79,12 +84,13 @@ def run_test(dut, stimulus_a, stimulus_b, op): expected_responses = [] actual_responses = [] for a, b in zip(stimulus_a, stimulus_b): + mid = randint(0, 6) af = Float32.from_bits(a) bf = Float32.from_bits(b) z = op(af, bf) - expected_responses.append(z.get_bits()) + expected_responses.append((z.get_bits(), mid)) #print (af, bf, z) - actual = yield from get_case(dut, a, b) + actual = yield from get_case(dut, a, b, mid) actual_responses.append(actual) if len(actual_responses) < len(expected_responses): @@ -93,7 +99,10 @@ def run_test(dut, stimulus_a, stimulus_b, op): for expected, actual, a, b in zip(expected_responses, actual_responses, stimulus_a, stimulus_b): - passed = match(expected, actual) + passed = match(expected[0], actual[0]) + if expected[1] != actual[1]: # check mid + print ("MID failed", expected[1], actual[1]) + sys.exit(0) if not passed: -- 2.30.2