From b8d3b2c68cbe01040fd9a8d7ec11615b53f21b14 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 19 May 2022 18:07:34 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 0a42edb63..6c5d7cb93 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -374,9 +374,26 @@ Pseudocode example (dest elwidth overrides not included): n2 = mask[2] & (mode[2] == creg[2]) n3 = mask[3] & (mode[3] == creg[3]) result = n0||n1||n2||n3 # 4-bit result - RT[60:63] = result # MSB0 numbering, 63 is LSB - If Rc: - CR0 = analyse(RT) + if RT.isvec: + # TODO: RT.elwidth override to be also added here + # yes, really, the CR's elwidth field determines + # the bit-packing into the INT! + if BB.elwidth == 0b00: + # pack 1 result into 64-bit registers + idx, boff = i, 0 + if BB.elwidth == 0b01: + # pack 2 results sequentially into INT registers + idx, boff = i//2, i%2 + if BB.elwidth == 0b10: + # pack 4 results sequentially into INT registers + idx, boff = i//t4, i%t4 + if BB.elwidth == 0b11: + # pack 8 results sequentially into INT registers + idx, boff = i//t8, i%t8 + else: + # exceeding VL=16 is UNDEFINED + idx, boff = 0, i + iregs[RT+idx][60-boff*4:63-boff*4] = result -- 2.30.2