From b8eaf0906af3edabf04c53bf354d481e7a44a4f5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 9 Sep 2012 20:51:15 +0200 Subject: [PATCH] Clean up --- migScope/tools/vcd.py | 4 +++- sim/tb_Migscope.py | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/migScope/tools/vcd.py b/migScope/tools/vcd.py index a4d00f4f..d7b1246f 100644 --- a/migScope/tools/vcd.py +++ b/migScope/tools/vcd.py @@ -1,5 +1,7 @@ +import sys import datetime +sys.path.append("../../") from migScope.tools.conv import * class Var: @@ -161,7 +163,7 @@ def main(): myvcd.add(Var("wire",3,"foo3")) myvcd.add(Var("wire",4,"foo4")) ramp = [i%128 for i in range(1024)] - myvcd.add(Var("wire",16,"sinus",ramp)) + myvcd.add(Var("wire",16,"ramp",ramp)) print(myvcd) if __name__ == '__main__': diff --git a/sim/tb_Migscope.py b/sim/tb_Migscope.py index 1d693356..8cf51345 100644 --- a/sim/tb_Migscope.py +++ b/sim/tb_Migscope.py @@ -9,7 +9,6 @@ import sys sys.path.append("../") from migScope import trigger, recorder - from migScope.tools.truthtable import * from migScope.tools.vcd import * @@ -76,11 +75,14 @@ def csr_transactions(trigger0, recorder0): #Arm yield TWrite(recorder0.address + 1, 1) - + # Wait Record to be done + ############################## global rec_done while not rec_done: yield None + # Read recorded data + ############################## global dat_rdy for t in range(64): yield TWrite(recorder0.address + 7, 1) -- 2.30.2