From b8fc2f3cea626254491c02090f9e97f23adc4e39 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 14:58:51 +0100
Subject: [PATCH]

---
 openpower/sv/cr_ops.mdwn | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index a3e3c7a89..3a6919033 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -109,10 +109,6 @@ Examples of the former type:
   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
   of BF to be tested is identified.
 
-This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
-Mode. This is unfortunste but unavoidable due to encoding pressure
-on SVP64.
-
 # Predicate-result Condition Register operations
 
 These are again slightly different compared to SVP64 arithmetic
-- 
2.30.2