From b901364fb05a5422c8cdee4394d77b22ce9cfee0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 3 Jun 2021 15:43:21 +0100 Subject: [PATCH] dummy PLL added with bypass, rename ref to ref_v due to ref being keyword --- libresoc/core.py | 1 + libresoc/pll.v | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 libresoc/pll.v diff --git a/libresoc/core.py b/libresoc/core.py index 853191f..6c39cd9 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -375,6 +375,7 @@ class LibreSoC(CPU): def add_sources(platform): cdir = os.path.dirname(__file__) platform.add_source(os.path.join(cdir, "libresoc.v")) + platform.add_source(os.path.join(cdir, "pll.v")) platform.add_source(os.path.join(cdir, "SPBlock_512W64B8W.v")) def do_finalize(self): diff --git a/libresoc/pll.v b/libresoc/pll.v new file mode 100644 index 0000000..9dc8428 --- /dev/null +++ b/libresoc/pll.v @@ -0,0 +1,10 @@ +module pll(input [0:0] ref_v, + output [0:0] div_out_test, + input [0:0] a0, + input [0:0] a1, + output [0:0] vco_test_ana, + output [0:0] out_v); + /* fake PLL */ + assign out_v = ref; +endmodule + -- 2.30.2