From b91c9727c26f26e05093b09b7febdf80bb89df0d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 20:28:54 +0100 Subject: [PATCH] set xer_ov.ok = 1 --- src/soc/fu/div/output_stage.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 0af52151..39a3bce1 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -32,6 +32,8 @@ class DivOutputStage(PipeModBase): def elaborate(self, platform): m = Module() comb = m.d.comb + + # convenience variables op = self.i.ctx.op abs_quotient = self.i.core.quotient_root fract_width = self.pspec.core_config.fract_width @@ -46,7 +48,9 @@ class DivOutputStage(PipeModBase): quotient_64 = self.quotient_64 remainder_64 = self.remainder_64 + # work out if sign of result is to be negative comb += self.quotient_neg.eq(dividend_neg ^ divisor_neg) + # follows rules for truncating division comb += self.remainder_neg.eq(dividend_neg) @@ -60,6 +64,8 @@ class DivOutputStage(PipeModBase): -abs_remainder, abs_remainder)) ] + # calculate overflow + self.o.xer_ov.ok.eq(1) xer_ov = self.o.xer_ov.data def calc_overflow(dive_abs_overflow, sign_bit_mask): -- 2.30.2