From b9450a8d71b2fa1d4d01cfe9063436681b5f79a6 Mon Sep 17 00:00:00 2001 From: klehman Date: Sat, 11 Sep 2021 20:53:31 -0400 Subject: [PATCH] added factory function for test class creation --- src/soc/simple/test/teststate.py | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py index 8d6c32bd..c51107ed 100644 --- a/src/soc/simple/test/teststate.py +++ b/src/soc/simple/test/teststate.py @@ -1,27 +1,14 @@ from openpower.decoder.power_enums import XER_bits -class State: - def __init__(self): - pass - - def get_intregs(self): - pass - - def get_crregs(self): - pass - - def get_xregs(self): - pass - - def get_pc(self): - pass +class State: def get_state(self): yield from self.get_intregs() yield from self.get_crregs() yield from self.get_xregs() yield from self.get_pc() + class SimState(State): def __init__(self, sim): self.sim = sim @@ -103,3 +90,13 @@ class HDLState(State): self.pc = yield self.state.r_ports['cia'].o_data self.pcl.append(self.pc) print("class hdl pc", hex(self.pc)) + + +def TestState(state_type, dut, state_dic): + state_factory = {'sim': SimState, 'hdl': HDLState} + state_class = state_factory[state_type] + state = state_class(state_dic[state_type]) + state.dut = dut + state.state_type = state_type + yield from state.get_state() + return state -- 2.30.2