From b96ce5f14e924694928f66f892981b71d4c0aa21 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 26 Apr 2023 07:50:41 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls014.mdwn | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/openpower/sv/rfc/ls014.mdwn b/openpower/sv/rfc/ls014.mdwn
index 4833e4f38..82050215c 100644
--- a/openpower/sv/rfc/ls014.mdwn
+++ b/openpower/sv/rfc/ls014.mdwn
@@ -87,6 +87,41 @@ Add the following entries to:
 * Book I 3.3.13 Fixed-Point Logical Instructions
 * Book I 1.6.1 and 1.6.2
 
+----------
+
+\newpage{}
+
+# Rationale
+
+## bmask
+
+Based on RVV masked set-before-first, set-after-first etc.
+and Intel and AMD Bitmanip instructions made generalised then
+advanced further to include masks, this is a single instruction
+covering 24 individual instructions in other ISAs.
+
+The patterns within the pseudocode for AMD TBM and x86 BMI1 are
+as follows:
+
+* first pattern A: two options `x` or `~x`
+* second pattern B: three options `|` `&` or `^`
+* third pattern C: four options `x+1`, `x-1`, `~(x+1)` or `(~x)+1`
+
+Thus it makes sense to create a single instruction
+that covers all of these.  A crucial addition that is essential
+for Scalable Vector usage as Predicate Masks, is the second mask parameter
+(RB).  The additional paramater, L, if set, will leave bits of RA masked
+by RB unaltered, otherwise those bits are set to zero. Note that when `RB=0`
+then instead of reading from the register file the mask is set to all ones.
+
+
+Executable pseudocode demo:
+
+```
+[[!inline pages="openpower/sv/bmask.py" quick="yes" raw="yes" ]]
+```
+
+
 ----------
 
 \newpage{}
-- 
2.30.2