From b98055330932a19997e68f2c935b0c7dfd90d9c1 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Tue, 13 Jun 2017 14:22:06 -0700 Subject: [PATCH] i965/cnl: Don't write to Cache Mode Register 1 on gen10+ With below optimizations gone in gen10+ we have nothing left out to write to CACHE_MODE_1: Float Blend Optimization Enable: This bit have been removed in gen10+ Partial Resolve Disable in VC: Recommendation is to always set this field to 0 in gen10+ and that's the default value of the bit. Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_state_upload.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 926597b6258..5e82c1b4ce8 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -60,8 +60,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); - /* Recommended optimization for Victim Cache eviction in pixel backend. */ - if (brw->gen >= 9) { + if (brw->gen == 9) { + /* Recommended optimizations for Victim Cache eviction and floating + * point blending. + */ BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(GEN7_CACHE_MODE_1); -- 2.30.2