From b9a492c39e9b295e09623322b1898e2fad01bed0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 16:11:59 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 370efc7fc..b9385b669 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -94,22 +94,25 @@ the next decade. with SVLR by SV-Branch-Conditional for exactly the same reason that NIA is swapped with LR -* Management Instructions +* Vector Management Instructions * **setvl** - Cray-style Scalar Vector Length instruction +* **svstep** - used for Vertical-First Mode and for enquiring about internal state * **svremap** - "tags" registers for activating REMAP * **svshape** - convenience instruction for quickly setting up Matrix, DCT, FFT and Parallel Reduction REMAP -* **svshape2** - additional convenience instruction to set up "Indexed" REMAP +* **svshape2** - additional convenience instruction to set up "Offset" REMAP (fits within svshape's XO encoding) -* **svindex** - +* **svindex** - convenience instruction for setting up "Indexed" REMAP. # SVP64 24-bit Prefix The SVP64 24-bit Prefix provides several options, too numerous to describe in this document. The primary options are: - +* element-width overrides, which dynamically redefine each SFFS or SFS Scalar prefixed + instruction to be 8-bit, 16-bit, 32-bit or 64-bit operands **without requiring new + 8/16/32 instructions** [^pseudorewrite] * Due to a concept called "Element-width Overrides -- 2.30.2