From b9a9d722263b7e32e962a37d3691c2a0f4ad4b96 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 7 Dec 2021 22:56:21 +0000 Subject: [PATCH] Changed jtag function imports to use test_jtag_tap, pad/core pin toggling not working yet --- src/spec/testing_stage1.py | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index 03c8c5d..d53f617 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -21,9 +21,12 @@ from nmigen.sim import Simulator, Delay, Settle, Tick, Passive from nmutil.util import wrap -from soc.debug.jtagutils import (jtag_read_write_reg, - jtag_srv, jtag_set_reset, - jtag_set_ir, jtag_set_get_dr) +#from soc.debug.jtagutils import (jtag_read_write_reg, +# jtag_srv, jtag_set_reset, +# jtag_set_ir, jtag_set_get_dr) + +from soc.debug.test.test_jtag_tap import (jtag_read_write_reg, + jtag_set_reset) from c4m.nmigen.jtag.tap import TAP, IOType from c4m.nmigen.jtag.bus import Interface as JTAGInterface @@ -644,11 +647,13 @@ def test_jtag_bs_chain(): print("JTAG I/O dictionary of core/pad signals:") print(top.jtag.ios.keys()) - top.jtag.ios['uart_0__rx'].core.i.eq(1) - top.jtag.ios['uart_0__rx'].pad.i.eq(0) - yield - top.jtag.ios['uart_0__rx'].core.i.eq(0) - top.jtag.ios['uart_0__rx'].pad.i.eq(1) + for i in range(0, 10): + top.jtag.ios['uart_0__rx'].core.i.eq(1) + top.jtag.ios['uart_0__rx'].pad.i.eq(0) + yield + top.jtag.ios['uart_0__rx'].core.i.eq(0) + top.jtag.ios['uart_0__rx'].pad.i.eq(1) + yield # Testing GPIO access #'gpio_0__gpio0__i', 'gpio_0__gpio0__o', 'gpio_0__gpio0__oe', -- 2.30.2