From b9bb36db96edb0a27b94dfba4c7347d360a2a69f Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 15 Sep 2022 19:40:48 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 66 +++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index ab5b8cb79..c9eb4e426 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -656,11 +656,11 @@ The only potential difficulty (solvable with a mapping table) is in fulfilling the "uniform suffix" requirement for `SVP64:EXT000-063` (and SVP64Single in future). Example: -| width | assembler | prefix? | 32-3 | suffix | description | -|-------|-----------|--------------|------|-----------|---------------| -| 32bit | fishmv | none | n/a | 345678| scalar EXT0nn | -| 64bit | ss.fishmv | 0x26!zero | 0b11 | 345678| scalar SVP64Single:EXT0nn | -| 64bit | sv.fishmv | 0x27nnnnnn | 0b11 | 345678| vector SVP64:EXT0nn | +| width | assembler | prefix? | 32-3 | suffix | description | +|-------|-----------|------------|------|-----------|---------------| +| 32bit | fishmv | none | n/a | 345678| scalar EXT0nn | +| 64bit | ss.fishmv | 0x26!zero | 0b11 | 345678| scalar SVP64Single:EXT0nn | +| 64bit | sv.fishmv | 0x27nnnnnn | 0b11 | 345678| vector SVP64:EXT0nn | Note that the suffix would be bits 0-31 for 32-bit, and 34-63 in 64-bit, where bits 2-31 of 32-bit Scalar are **required** to be the same as 34-63 @@ -678,9 +678,17 @@ minimum. Note that this has no effect on or relation to other `RESERVED` uses of bits 32-3 -(0b00/0b01/0b10) +(0b00/0b01/0b10). However, it is important to note that in the +EXT300-363 range, Simple-V will never under any circumstances be +applicable to these opcodes. +If EXT300-363 is ever considered at all by a future RFC, +potential EXT348-363 +is strongly recommended to +always be illegal instructions so as not to conflict with bits +32-33 being 0b11 for Simple-V. \newpage{} + **EXT000-EXT063** These are Scalar word-encodings. Often termed "v3.0 Scalar" in this document @@ -690,7 +698,7 @@ Power ISA v3.1 Section 1.6.3 Book I calls it a "defined word". |--------|--------| | PO | EXT000-063 Scalar (v3.0 or v3.1) operation | -**RESERVED2 / EXT300-363** bit6=old bit7=scalar +**RESERVED2 / EXT300-347** bit6=old bit7=scalar This is entirely at the discretion of the ISA WG. Libre-SOC is *not* proposing the addition of EXT300-363: it is merely a possibility for @@ -703,7 +711,8 @@ for other purposes. | 0-5 | 6 | 7 | 8-31 | 32-63 | |--------|---|---|-------|---------| -| PO (9)?| 1 | 0 | 0000 | EXT300-363 or `RESERVED1` | +| PO (9)?| 1 | 0 | 0000 | EXT300-347 or `RESERVED1` | +| PO (9)?| 1 | 0 | 0000 | EXT348-363 Illegal (always) | **{EXT200-263}** bit6=new bit7=scalar @@ -803,13 +812,44 @@ across the board (in the Scalar Suffix side, irrespective of Prefix), some allocated to Simple-V, some not. -**example, legal (sort-of)* +**illegal due to missing* -* 32bit fishmv EXT0nn 0x12345678 or - 64bit scalar EXT2nn 0x240000000 0x12345678 -* vector RESERVEDunallocated 0x27nnnnnn 0x12345678 +| width | assembler | prefix? | suffix | description | +|-------|-----------|--------------|-----------|---------------| +| 32bit | fishmv | none | 0x12345678| scalar EXT0nn | +| 64bit | ss.fishmv | 0x26!zero | 0x12345678| scalar SVP64Single:EXT0nn | +| 64bit | unallocated | 0x27nnnnnn | 0x12345678| vector SVP64:EXT0nn | + +This is illegal because the instruction is possible to Vectorise, +therefore it should be **defined** as Vectoriseable. + +**illegal due to unvectoriseable* -this is sort-of-not-illegal because the space is automatically reserved for trap-and-emulate of Vector fishmv by Lower SV Compliancy Levels. +| width | assembler | prefix? | suffix | description | +|-------|-----------|--------------|-----------|---------------| +| 32bit | mtmsr | none | 0x12345678| scalar EXT0nn | +| 64bit | ss.mtmsr | 0x26!zero | 0x12345678| scalar SVP64Single:EXT0nn | +| 64bit | sv.mtmsr | 0x27nnnnnn | 0x12345678| vector SVP64:EXT0nn | + +This is illegal because the instruction `mtmsr` is not possible to Vectorise, +at all. This does **not** convey an opportunity to allocate the +space to an alternative instruction. + +**illegal unvectoriseable in EXT2nn** + +| width | assembler | prefix? | suffix | description | +|-------|-----------|--------------|-----------|---------------| +| 64bit | mtmsr2 | 0x24000000 | 0x12345678| scalar EXT2nn | +| 64bit | ss.mtmsr2 | 0x24!zero | 0x12345678| scalar SVP64Single:EXT2nn | +| 64bit | sv.mtmsr2 | 0x26nnnnnn | 0x12345678| vector SVP64:EXT2nn | + +For a given hypothetical `mtmsr2` which is inherently Unvectoriseable +whilst it may be put into the scalar EXT2nn space it may **not** be +allocated in the Vector space. As with Unvectoriseable EXT0nn opcodes +this does not convey the right to use the 0x24/0x26 space for alternative +opcodes. This hypothetical Unvectoriseable operation would be better off +being allocated as EXT001 Prefixed, EXT000-063, or hypothetically in +EXT300-363. **example ILLEGAL:** -- 2.30.2