From b9c7379c5a3064b3238a5a37d923b206a01a2e84 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 28 Jul 2020 15:49:06 -0700 Subject: [PATCH] format code --- src/soc/fu/div/test/runner.py | 4 ++-- src/soc/fu/div/test/test_all_pipe_caller.py | 2 -- src/soc/fu/div/test/test_pipe_caller.py | 5 ++--- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py index 04f837b6..ee4d842d 100644 --- a/src/soc/fu/div/test/runner.py +++ b/src/soc/fu/div/test/runner.py @@ -16,6 +16,7 @@ from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind import power_instruction_analyzer as pia + def log_rand(n, min_val=1): logrange = random.randint(1, n) return random.randint(min_val, (1 << logrange)-1) @@ -100,7 +101,7 @@ def set_alu_inputs(alu, dec2, sim): class DivRunner(unittest.TestCase): def __init__(self, test_data, div_pipe_kind=None): - print ("DivRunner", test_data, div_pipe_kind) + print("DivRunner", test_data, div_pipe_kind) super().__init__("run_all") self.test_data = test_data self.div_pipe_kind = div_pipe_kind @@ -301,4 +302,3 @@ class DivRunner(unittest.TestCase): print("so, ov", so_ok, ov_ok) self.assertEqual(ov_ok, False, code) self.assertEqual(so_ok, False, code) - diff --git a/src/soc/fu/div/test/test_all_pipe_caller.py b/src/soc/fu/div/test/test_all_pipe_caller.py index 319f1ef8..bf62cd5f 100644 --- a/src/soc/fu/div/test/test_all_pipe_caller.py +++ b/src/soc/fu/div/test/test_all_pipe_caller.py @@ -53,7 +53,5 @@ if __name__ == "__main__": suite.addTest(DivRunner(DivTestLong().test_data, DivPipeKind.FSMDivCore)) suite.addTest(DivRunner(DivTestLong().test_data, DivPipeKind.SimOnly)) - runner = unittest.TextTestRunner() runner.run(suite) - diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 6b02d0d9..88e72155 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -85,7 +85,7 @@ class DivTestCases(TestAccumulatorBase): with Program(lst, bigendian) as prog: self.add_case(prog, initial_regs) - def case_8_fsm_regression(self): # FSM result is "36" not 6 + def case_8_fsm_regression(self): # FSM result is "36" not 6 lst = ["divwu. 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 18 @@ -93,7 +93,7 @@ class DivTestCases(TestAccumulatorBase): with Program(lst, bigendian) as prog: self.add_case(prog, initial_regs) - def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11 + def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11 lst = ["divw. 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 1 @@ -173,4 +173,3 @@ if __name__ == "__main__": runner = unittest.TextTestRunner() runner.run(suite) - -- 2.30.2