From b9d6c656e10bade2b4dd3c68b6e86d1f849abff8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Feb 2022 19:35:14 +0000 Subject: [PATCH] add wishbone downconvert "skip" of slave sel so that action is not taken --- src/soc/bus/wb_downconvert.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/bus/wb_downconvert.py b/src/soc/bus/wb_downconvert.py index 77564f2f..2b03d56b 100644 --- a/src/soc/bus/wb_downconvert.py +++ b/src/soc/bus/wb_downconvert.py @@ -52,6 +52,7 @@ class WishboneDownConvert(Elaboratable): counter_done = Signal() comb += counter_done.eq(counter == ratio-1) comb += cur_counter.eq(counter) + skip = Signal() # Main FSM with m.FSM() as fsm: @@ -67,11 +68,12 @@ class WishboneDownConvert(Elaboratable): with m.State("WRITE"): comb += write.eq(1) with m.If(master.stb & master.cyc): + comb += skip.eq(slave.sel == 0) comb += slave.we.eq(1) comb += slave.cyc.eq(1) comb += slave.stb.eq(1) - with m.If(slave.ack): - comb += cur_counter.eq(counter + 1) + with m.If(slave.ack | skip): + comb += cur_counter.eq(counter + 1) # TODO use Picker sync += counter.eq(cur_counter) with m.If(counter_done): comb += master.ack.eq(1) @@ -82,10 +84,11 @@ class WishboneDownConvert(Elaboratable): with m.State("READ"): comb += read.eq(1) with m.If(master.stb & master.cyc): + comb += skip.eq(slave.sel == 0) comb += slave.cyc.eq(1) comb += slave.stb.eq(1) - with m.If(slave.ack): - comb += cur_counter.eq(counter + 1) + with m.If(slave.ack | skip): + comb += cur_counter.eq(counter + 1) # TODO use Picker sync += counter.eq(cur_counter) with m.If(counter_done): comb += master.ack.eq(1) @@ -115,7 +118,7 @@ class WishboneDownConvert(Elaboratable): # read Datapath - uses cached_data and master.dat_r as a shift-register. # by the time "counter" is done (counter_done) this is complete comb += shift_reg.eq(Cat(cached_data[dw_to:], slave.dat_r)) - with m.If(read & slave.ack): + with m.If(read & (slave.ack | skip)): sync += cached_data.eq(shift_reg) -- 2.30.2