From b9dc340b7567404c76b6a7e042c2fa3c59787515 Mon Sep 17 00:00:00 2001
From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Fri, 27 Sep 2013 02:17:19 -0700
Subject: [PATCH] Added commit logging (--enable-commitlog). Also fixed disasm
 bug.

---
 riscv/decode.h     | 27 +++++++++++++++++++++++++++
 riscv/disasm.cc    | 12 ++++++------
 riscv/processor.cc | 16 ++++++++++++++++
 riscv/riscv.ac     |  5 +++++
 4 files changed, 54 insertions(+), 6 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index bde921f..7cf7eac 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -13,6 +13,7 @@
 #include "pcr.h"
 #include "config.h"
 #include "common.h"
+#include <cinttypes>
 
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
@@ -96,10 +97,36 @@ private:
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
 #define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_RD 
+  #define WRITE_RD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        reg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->XPR.write(insn.rd(), wdata); \
+      })
+#endif
+
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
 #define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+ 
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_FRD 
+  #define WRITE_FRD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        freg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->FPR.write(insn.rd(), wdata); \
+      })
+#endif
+ 
+
+
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())
diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 1271a18..caf4ff4 100644
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -226,12 +226,12 @@ std::string disassembler::disassemble(insn_t insn)
 
 disassembler::disassembler()
 {
-  const uint32_t mask_rd = 0x1fUL << 27;
-  const uint32_t match_rd_ra = 1UL << 27;
-  const uint32_t mask_rs1 = 0x1fUL << 22;
-  const uint32_t match_rs1_ra = 1UL << 22;
-  const uint32_t mask_rs2 = 0x1fUL << 17;
-  const uint32_t mask_imm = 0xfffUL << 10;
+  const uint32_t mask_rd = 0x1fUL << 7;
+  const uint32_t match_rd_ra = 1UL << 7;
+  const uint32_t mask_rs1 = 0x1fUL << 15;
+  const uint32_t match_rs1_ra = 1UL << 15;
+  const uint32_t mask_rs2 = 0x1fUL << 15;
+  const uint32_t mask_imm = 0xfffUL << 20;
 
   #define DECLARE_INSN(code, match, mask) \
    const uint32_t match_##code = match; \
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 839c846..5c0d784 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -107,6 +107,22 @@ void processor_t::step(size_t n, bool noisy)
         npc = fetch.func(this, fetch.insn.insn, npc); \
       } while(0)
 
+    
+    // special execute_insn  for commit log dumping
+#ifdef RISCV_ENABLE_COMMITLOG
+    //static disassembler disasmblr; 
+    #undef execute_insn 
+    #define execute_insn(noisy) \
+      do { \
+        mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
+        if(noisy) disasm(fetch.insn.insn, npc); \
+        bool in_spvr = state.sr & SR_S; \
+        if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
+        /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
+        npc = fetch.func(this, fetch.insn.insn, npc); \
+      } while(0)
+#endif
+
     if(noisy) for( ; i < n; i++) // print out instructions as we go
       execute_insn(true);
     else 
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 335a0bf..cfb9d71 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -20,3 +20,8 @@ AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
 AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
+                           
+AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit log generation]))
+AS_IF([test "x$enable_commitlog" = "xyes"], [
+  AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation])
+])
-- 
2.30.2