From b9e3e870693ac8f118c4350a7d575a776cc9caf4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 1 May 2016 13:32:33 +0200 Subject: [PATCH] radeonsi: just read tile mode arrays in SDMA setup MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/cik_sdma.c | 79 +++++++++---------------- 1 file changed, 28 insertions(+), 51 deletions(-) diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 07a7d945301..2a996c1e2d4 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -31,18 +31,6 @@ #include "util/u_format.h" -static uint32_t cik_micro_tile_mode(struct si_screen *sscreen, unsigned tile_mode) -{ - if (sscreen->b.info.si_tile_mode_array_valid) { - uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode]; - - return G_009910_MICRO_TILE_MODE_NEW(gb_tile_mode); - } - - /* The kernel cannod return the tile mode array. Guess? */ - return V_009910_ADDR_SURF_THIN_MICRO_TILING; -} - static void cik_sdma_do_copy_buffer(struct si_context *ctx, struct pipe_resource *dst, struct pipe_resource *src, @@ -113,19 +101,26 @@ static void cik_sdma_copy_tile(struct si_context *ctx, unsigned bpe) { struct radeon_winsys_cs *cs = ctx->b.dma.cs; - struct si_screen *sscreen = ctx->screen; struct r600_texture *rsrc = (struct r600_texture*)src; struct r600_texture *rdst = (struct r600_texture*)dst; - struct r600_texture *rlinear, *rtiled; - unsigned linear_lvl, tiled_lvl; + unsigned dst_mode = rdst->surface.level[dst_level].mode; + unsigned src_mode = rsrc->surface.level[src_level].mode; + bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; + struct r600_texture *rlinear = detile ? rdst : rsrc; + struct r600_texture *rtiled = detile ? rsrc : rdst; + unsigned linear_lvl = detile ? dst_level : src_level; + unsigned tiled_lvl = detile ? src_level : dst_level; + struct radeon_info *info = &ctx->screen->b.info; + unsigned index = rtiled->surface.tiling_index[tiled_lvl]; + unsigned macro_index = rtiled->surface.macro_tile_index; + unsigned tile_mode = info->si_tile_mode_array[index]; + unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; unsigned array_mode, lbpe, pitch_tile_max, slice_tile_max, size; - unsigned ncopy, height, cheight, detile, i, src_mode, dst_mode; + unsigned ncopy, height, cheight, i; unsigned sub_op, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt; uint64_t base, addr; - unsigned pipe_config, tile_mode_index; + unsigned pipe_config; - dst_mode = rdst->surface.level[dst_level].mode; - src_mode = rsrc->surface.level[src_level].mode; assert(dst_mode != src_mode); assert(src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED || dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED); @@ -133,31 +128,25 @@ static void cik_sdma_copy_tile(struct si_context *ctx, lbpe = util_logbase2(bpe); pitch_tile_max = ((pitch / bpe) / 8) - 1; - detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED; - rlinear = detile ? rdst : rsrc; - rtiled = detile ? rsrc : rdst; - linear_lvl = detile ? dst_level : src_level; - tiled_lvl = detile ? src_level : dst_level; - assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format)); - array_mode = si_array_mode(rtiled->surface.level[tiled_lvl].mode); + array_mode = G_009910_ARRAY_MODE(tile_mode); slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x * rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1; height = rlinear->surface.level[linear_lvl].nblk_y; base = rtiled->surface.level[tiled_lvl].offset; addr = rlinear->surface.level[linear_lvl].offset; - bank_h = cik_bank_wh(rtiled->surface.bankh); - bank_w = cik_bank_wh(rtiled->surface.bankw); - mt_aspect = cik_macro_tile_aspect(rtiled->surface.mtilea); - tile_split = cik_tile_split(rtiled->surface.tile_split); - tile_mode_index = si_tile_mode_index(rtiled, tiled_lvl, false); - nbanks = si_num_banks(sscreen, rtiled); + bank_h = G_009990_BANK_HEIGHT(macro_mode); + bank_w = G_009990_BANK_WIDTH(macro_mode); + mt_aspect = G_009990_MACRO_TILE_ASPECT(macro_mode); + /* Non-depth modes don't have TILE_SPLIT set. */ + tile_split = util_logbase2(rtiled->surface.tile_split >> 6); + nbanks = G_009990_NUM_BANKS(macro_mode); base += rtiled->resource.gpu_address; addr += rlinear->resource.gpu_address; - pipe_config = cik_db_pipe_config(sscreen, tile_mode_index); - mt = cik_micro_tile_mode(sscreen, tile_mode_index); + pipe_config = G_009910_PIPE_CONFIG(tile_mode); + mt = G_009910_MICRO_TILE_MODE_NEW(tile_mode); size = (copy_height * pitch) / 4; cheight = copy_height; @@ -283,23 +272,11 @@ void cik_sdma_copy(struct pipe_context *ctx, y_align = 8; break; case RADEON_SURF_MODE_2D: { - unsigned mtilew, mtileh, num_banks; - - switch (si_num_banks(sctx->screen, rsrc)) { - case V_02803C_ADDR_SURF_2_BANK: - default: - num_banks = 2; - break; - case V_02803C_ADDR_SURF_4_BANK: - num_banks = 4; - break; - case V_02803C_ADDR_SURF_8_BANK: - num_banks = 8; - break; - case V_02803C_ADDR_SURF_16_BANK: - num_banks = 16; - break; - } + unsigned mtilew, mtileh; + struct radeon_info *info = &sctx->screen->b.info; + unsigned macro_index = rsrc->surface.macro_tile_index; + unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; + unsigned num_banks = 2 << G_009990_NUM_BANKS(macro_mode); mtilew = (8 * rsrc->surface.bankw * sctx->screen->b.info.num_tile_pipes) * -- 2.30.2