From b9f83db94ca5d26646c0f57c3320666d5a5e724f Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Wed, 10 Jun 2020 12:48:18 +0200 Subject: [PATCH] Add self._bridge to m.submodules (fixing #4) --- gram/core/__init__.py | 2 ++ gram/phy/ecp5ddrphy.py | 2 ++ 2 files changed, 4 insertions(+) diff --git a/gram/core/__init__.py b/gram/core/__init__.py index 5a07556..16b022e 100644 --- a/gram/core/__init__.py +++ b/gram/core/__init__.py @@ -52,6 +52,8 @@ class gramCore(Peripheral, Elaboratable): def elaborate(self, platform): m = Module() + m.submodules += self._bridge + m.submodules += self.dfii m.d.comb += self.dfii.master.connect(self._phy.dfi) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 6e1ec04..cf1a9c9 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -155,6 +155,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable): def elaborate(self, platform): m = Module() + m.submodules += self._bridge + tck = 2/(2*2*self._sys_clk_freq) nphases = 2 databits = len(self.pads.dq.oe) -- 2.30.2