From b9fb4d4870dd45c552fd4cd5e531e9626754f19f Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 17:13:50 -0400
Subject: [PATCH] Make memtest work with 8 memtesters

src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
---
 src/mem/physical.cc                     |  2 +-
 src/python/m5/objects/PhysicalMemory.py |  1 +
 tests/configs/memtest.py                | 10 ++++++++--
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 070693442..96d78bd99 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -231,7 +231,7 @@ PhysicalMemory::getPort(const std::string &if_name, int idx)
         port = new MemoryPort(name() + "-port", this);
         return port;
     } else if (if_name == "functional") {
-        /* special port for functional writes at startup. */
+        /* special port for functional writes at startup. And for memtester */
         return new MemoryPort(name() + "-funcport", this);
     } else {
         panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index dd3ffd651..4e097543d 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -5,6 +5,7 @@ from MemObject import *
 class PhysicalMemory(MemObject):
     type = 'PhysicalMemory'
     port = Port("the access port")
+    functional = Port("Functional Access Port")
     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
     file = Param.String('', "memory mapped file")
     latency = Param.Latency(Parent.clock, "latency of an access")
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index cfcefbcb9..c5cd0246d 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -51,7 +51,8 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
-nb_cores = 1
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
 cpus = [ MemTest(max_loads=1e12) for i in xrange(nb_cores) ]
 
 # system simulated
@@ -66,12 +67,17 @@ system.l2c.cpu_side = system.toL2Bus.port
 # connect l2c to membus
 system.l2c.mem_side = system.membus.port
 
+which_port = 0
 # add L1 caches
 for cpu in cpus:
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.port
-    system.funcmem.port = cpu.functional
+    if  which_port == 0:
+         system.funcmem.port = cpu.functional
+         which_port = 1
+    else:
+         system.funcmem.functional = cpu.functional
 
 
 # connect memory to membus
-- 
2.30.2