From b9fc8a3953430df41cf4e4b1287fc559b428052b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 11 Mar 2020 18:18:14 +0000 Subject: [PATCH] fix more imports --- src/soc/minerva/units/fetch.py | 4 ++-- src/soc/minerva/units/loadstore.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index b140aa20..4f7eb06e 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -1,8 +1,8 @@ -from nmigen import Elaboratable, Module, Signal, Record +from nmigen import Elaboratable, Module, Signal, Record, Const, Mux from nmigen.utils import log2_int from ..cache import L1Cache -from ..wishbone import wishbone_layout +from ..wishbone import wishbone_layout, WishboneArbiter, Cycle __all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"] diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index ac2a0426..34698514 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -1,10 +1,10 @@ -from nmigen import Elaboratable, Module, Signal, Record, Cat +from nmigen import Elaboratable, Module, Signal, Record, Cat, Const, Mux from nmigen.utils import log2_int from nmigen.lib.fifo import SyncFIFO from ..cache import L1Cache from ..isa import Funct3 -from ..wishbone import wishbone_layout +from ..wishbone import wishbone_layout, WishboneArbiter, Cycle __all__ = ["DataSelector", "LoadStoreUnitInterface", "BareLoadStoreUnit", "CachedLoadStoreUnit"] -- 2.30.2