From ba05e1926331dded3096eb30b73adc7e10756452 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Dec 2021 23:49:06 +0000 Subject: [PATCH] add link to XICS bugreport --- src/soc/interrupts/xics.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py index ede33a1b..d1bc0296 100644 --- a/src/soc/interrupts/xics.py +++ b/src/soc/interrupts/xics.py @@ -16,6 +16,9 @@ # highest priority interrupt currently presented (which is allowed # via XICS) # +# Bugreports: +# +# * https://bugs.libre-soc.org/show_bug.cgi?id=407 """ from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux from nmutil.iocontrol import RecordObject -- 2.30.2