From ba10c1a424d77f93a5125878fa779b5504142c10 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 30 Mar 2023 01:10:39 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls010.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 3ed1b9876..41b01a266 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -1152,6 +1152,7 @@ which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to add
 the modes typically found in *all* Scalable Vector ISAs, without changing
 the behaviour of the underlying Base (Scalar) v3.0B operations in any way.
+(The sole apparent exception is Post-Increment Mode on LD/ST-update instructions)
 
 ## Modes overview
 
-- 
2.30.2