From ba121efd22820aeacb25847cb503883827f81e18 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 17 Feb 2021 18:30:20 +0100 Subject: [PATCH] add wishbone signals to gtkwave output --- src/soc/simple/test/test_runner.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 3e22a8a0..77621ae0 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -376,7 +376,13 @@ class TestRunner(FHDLTestCase): 'core.fus.mmu0.alu_mmu0.debug0[3:0]', 'core.fus.mmu0.alu_mmu0.mmu.state', 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]', - 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]' + 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]', + {'comment': 'wishbone_memory'}, + 'core.fus.mmu0.alu_mmu0.dcache.stb', + 'core.fus.mmu0.alu_mmu0.dcache.cyc', + 'core.fus.mmu0.alu_mmu0.dcache.we', + 'core.fus.mmu0.alu_mmu0.dcache.ack', + 'core.fus.mmu0.alu_mmu0.dcache.stall,' ] write_gtkw("issuer_simulator.gtkw", -- 2.30.2