From ba148813d7c5f90f2a46819c33611e760edf86ed Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 13 Jan 2020 16:14:24 -0800 Subject: [PATCH] iris: Support multiple chained batches. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit There was never much point in artificially limiting chaining to two batches - we can trivially support arbitrary length chains. Currently, we should only ever have 1 or 2, but this may change. Reviewed-by: Tapani Pälli Tested-by: Marge Bot Part-of: --- src/gallium/drivers/iris/iris_batch.c | 40 +++++++++++++-------------- src/gallium/drivers/iris/iris_batch.h | 6 +++- 2 files changed, 25 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c index 2b5c62d4277..120aaf9cbd9 100644 --- a/src/gallium/drivers/iris/iris_batch.c +++ b/src/gallium/drivers/iris/iris_batch.c @@ -370,6 +370,7 @@ iris_batch_reset(struct iris_batch *batch) iris_bo_unreference(batch->bo); batch->primary_batch_size = 0; + batch->total_chained_batch_size = 0; batch->contains_draw = false; batch->decoder.surface_base = batch->last_surface_base_address; @@ -430,30 +431,37 @@ iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate) } } +static void +record_batch_sizes(struct iris_batch *batch) +{ + unsigned batch_size = iris_batch_bytes_used(batch); + + VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch->map, batch_size)); + + if (batch->bo == batch->exec_bos[0]) + batch->primary_batch_size = batch_size; + + batch->total_chained_batch_size += batch_size; +} + void iris_chain_to_new_batch(struct iris_batch *batch) { - /* We only support chaining a single time. */ - assert(batch->bo == batch->exec_bos[0]); - - VG(void *map = batch->map); uint32_t *cmd = batch->map_next; uint64_t *addr = batch->map_next + 4; batch->map_next += 12; + record_batch_sizes(batch); + /* No longer held by batch->bo, still held by validation list */ iris_bo_unreference(batch->bo); - batch->primary_batch_size = iris_batch_bytes_used(batch); create_batch(batch); /* Emit MI_BATCH_BUFFER_START to chain to another batch. */ *cmd = (0x31 << 23) | (1 << 8) | (3 - 2); *addr = batch->bo->gtt_offset; - - VG(VALGRIND_CHECK_MEM_IS_DEFINED(map, batch->primary_batch_size)); } - static void add_aux_map_bos_to_batch(struct iris_batch *batch) { @@ -493,10 +501,8 @@ iris_finish_batch(struct iris_batch *batch) map[0] = (0xA << 23); batch->map_next += 4; - VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch->map, iris_batch_bytes_used(batch))); - if (batch->bo == batch->exec_bos[0]) - batch->primary_batch_size = iris_batch_bytes_used(batch); + record_batch_sizes(batch); } /** @@ -644,17 +650,11 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line) if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT | DEBUG_PIPE_CONTROL))) { - int bytes_for_commands = iris_batch_bytes_used(batch); - int second_bytes = 0; - if (batch->bo != batch->exec_bos[0]) { - second_bytes = bytes_for_commands; - bytes_for_commands += batch->primary_batch_size; - } - fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5d+%5db (%0.1f%%) " + fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) " "(cmds), %4d BOs (%0.1fMb aperture)\n", file, line, batch_name_to_string(batch->name), batch->hw_ctx_id, - batch->primary_batch_size, second_bytes, - 100.0f * bytes_for_commands / BATCH_SZ, + batch->total_chained_batch_size, + 100.0f * batch->total_chained_batch_size / BATCH_SZ, batch->exec_count, (float) batch->aperture_space / (1024 * 1024)); diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h index 3912541c6dd..42c0f3e787a 100644 --- a/src/gallium/drivers/iris/iris_batch.h +++ b/src/gallium/drivers/iris/iris_batch.h @@ -67,9 +67,13 @@ struct iris_batch { struct iris_bo *bo; void *map; void *map_next; - /** Size of the primary batch if we've moved on to a secondary. */ + + /** Size of the primary batch being submitted to execbuf (in bytes). */ unsigned primary_batch_size; + /** Total size of all chained batches (in bytes). */ + unsigned total_chained_batch_size; + /** Last Surface State Base Address set in this hardware context. */ uint64_t last_surface_base_address; -- 2.30.2