From ba4ca41319070e25bc823937c46cc6e3f05c505b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Nov 2021 16:11:48 +0000 Subject: [PATCH] fix regfile port names for "fast" port access (regreduce=False) --- src/soc/experiment/pi2ls.py | 1 + src/soc/regfile/regfiles.py | 3 +++ src/soc/simple/core.py | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index cccb2133..2e8643da 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -47,6 +47,7 @@ class Pi2LSUI(PortInterfaceBase): self.valid_l = SRLatch(False, name="valid") def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): + print("pi2lsui TODO, implement is_dcbz") m.d.comb += self.valid_l.s.eq(1) m.d.comb += self.lsui.x_mask_i.eq(mask) m.d.comb += self.lsui.x_addr_i.eq(addr) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index dd7e3a76..93d94226 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -149,6 +149,9 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray): } if not self.regreduce_en: r_port_spec['fast2'] = "src2" + r_port_spec['fast3'] = "src3" + w_port_spec['fast2'] = "dest2" + w_port_spec['fast3'] = "dest3" return w_port_spec, r_port_spec diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 78e83976..d0149064 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -100,8 +100,8 @@ class NonProductionCore(ControlBase): mmu = self.fus.get_fu('mmu0') print ("core pspec", pspec.ldst_ifacetype) print ("core mmu", mmu) - print ("core lsmem.lsi", l0.cmpi.lsmem.lsi) if mmu is not None: + print ("core lsmem.lsi", l0.cmpi.lsmem.lsi) mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi) # register files (yes plural) -- 2.30.2