From ba71d502282cf9195bcefa1496d5bf3feb3e05ba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Nov 2018 08:55:04 +0000 Subject: [PATCH] add CSR_USVCFG set/get --- riscv/processor.cc | 9 +++++++++ riscv/sv.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 44cedc6..0161abe 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -509,6 +509,13 @@ void processor_t::set_csr(int which, reg_t val) reg_t destoffs = get_field(val, SV_STATE_DESTOFFS); state.sv().srcoffs = std::min(srcoffs , state.sv().vl-1); state.sv().destoffs = std::min(destoffs, state.sv().vl-1); + int state_bank = get_field(val, SV_STATE_BANK); + int state_size = get_field(val, SV_STATE_SIZE); + set_csr(CSR_USVCFG, state_bank | (state_size << 3)); + break; + } + case CSR_USVCFG: + { int old_bank = state.sv().state_bank; int old_size = state.sv().state_size; state.sv().state_bank = get_field(val, SV_STATE_BANK); @@ -850,6 +857,8 @@ reg_t processor_t::get_csr(int which) #ifdef SPIKE_SIMPLEV case CSR_USVVL: return state.sv().vl; + case CSR_USVCFG: + return (state.sv().state_bank) | (state.sv().state_size<<3); case CSR_USVSTATE: return (state.sv().vl-1) | ((state.sv().mvl-1)<<6) | (state.sv().srcoffs<<12) | (state.sv().destoffs<<18) | diff --git a/riscv/sv.h b/riscv/sv.h index 00f274c..d5db778 100644 --- a/riscv/sv.h +++ b/riscv/sv.h @@ -111,4 +111,7 @@ typedef struct { #define SV_STATE_BANK (0x7<<24) #define SV_STATE_SIZE (0x3<<27) +#define SV_CFG_BANK (0x7) +#define SV_CFG_SIZE (0x3<<3) + #endif -- 2.30.2