From ba81232a9cd47ba5e98c7fd83bd93cd49e38ee55 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 26 Oct 2020 16:47:09 +0000 Subject: [PATCH] --- openpower/sv/predication.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn index c5bd20a12..7c0eaef0e 100644 --- a/openpower/sv/predication.mdwn +++ b/openpower/sv/predication.mdwn @@ -43,7 +43,7 @@ Adding a full set special vector opcodes just for manipulating predicate masks a this involves treating each CR as providing one bit of predicate. If there is limited space in SVPrefix it will be a fixed bit (bit 0) -otherwise it may be selected (bit 0 to 3 of the CR) +otherwise it may be selected (bit 0 to 3 of the CR) through a firld in the opcode. the crucial advantage of this proposal is that the Function Units can have one more register (a CR) added as their Read Dependency Hazards -- 2.30.2