From ba87b6762797155bedc73628e7d0138ed3295bd8 Mon Sep 17 00:00:00 2001 From: R Veera Kumar Date: Tue, 23 Nov 2021 16:48:15 +0530 Subject: [PATCH] Add expected state to case_extsb in alu_cases unit test --- src/openpower/test/alu/alu_cases.py | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py index 2afff938..3bde8e27 100644 --- a/src/openpower/test/alu/alu_cases.py +++ b/src/openpower/test/alu/alu_cases.py @@ -460,7 +460,32 @@ class ALUTestCase(TestAccumulatorBase): print(lst) initial_regs = [0] * 32 initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) + + e = ExpectedState(pc=4) + e.intregs[1] = initial_regs[1] + if choice == "extsb": + s = ((initial_regs[1] & 0x1000_0000_0000_0080)>>7)&0x1 + if s == 1: + value = 0xffff_ffff_ffff_ff<<8 + else: + value = 0x0 + e.intregs[3] = value | (initial_regs[1] & 0xff) + elif choice == "extsh": + s = ((initial_regs[1] & 0x1000_0000_0000_8000)>>15)&0x1 + if s == 1: + value = 0xffff_ffff_ffff<<16 + else: + value = 0x0 + e.intregs[3] = value | (initial_regs[1] & 0xffff) + else: + s = ((initial_regs[1] & 0x1000_0000_8000_0000)>>31)&0x1 + if s == 1: + value = 0xffff_ffff<<32 + else: + value = 0x0 + e.intregs[3] = value | (initial_regs[1] & 0xffff_ffff) + + self.add_case(Program(lst, bigendian), initial_regs, expected=e) def case_cmpeqb(self): lst = ["cmpeqb cr1, 1, 2"] -- 2.30.2