From ba9e6314deefb00a13e5bb25575e4ccdb713faec Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 27 Oct 2011 04:05:27 -0700 Subject: [PATCH] changed page size to 8KB --- riscv/mmu.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/riscv/mmu.h b/riscv/mmu.h index fb186ee..d9a1ce3 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -10,8 +10,8 @@ class processor_t; // virtual memory configuration typedef reg_t pte_t; -const reg_t LEVELS = 4; -const reg_t PGSHIFT = 12; +const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2; +const reg_t PGSHIFT = 13; const reg_t PGSIZE = 1 << PGSHIFT; const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2); const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT; @@ -28,8 +28,7 @@ const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT; #define PTE_SW 0x100 // Supervisor Read permission #define PTE_SR 0x200 // Supervisor Write permission #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) -#define PTE_PERM_SHIFT 4 -#define PTE_PPN_SHIFT 12 // LSB of physical page number in the PTE +#define PTE_PPN_SHIFT 13 // LSB of physical page number in the PTE // this class implements a processor's port into the virtual memory system. // an MMU and instruction cache are maintained for simulator performance. -- 2.30.2