From baac5ec3d1e57c33baba0f4200a4a9af5efeceb5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Jul 2019 17:07:16 +0100 Subject: [PATCH] big (single-purpose) update: move width arg into pspec --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 13 ++++----- src/ieee754/fcvt/pipeline.py | 37 ++++++++++++-------------- src/ieee754/fpadd/add0.py | 14 +++++----- src/ieee754/fpadd/add1.py | 9 +++---- src/ieee754/fpadd/addstages.py | 13 +++++---- src/ieee754/fpadd/align.py | 26 +++++++++--------- src/ieee754/fpadd/pipeline.py | 17 ++++++------ src/ieee754/fpadd/specialcases.py | 23 ++++++++-------- src/ieee754/fpcommon/corrections.py | 7 +++-- src/ieee754/fpcommon/denorm.py | 15 +++++------ src/ieee754/fpcommon/getop.py | 9 +++---- src/ieee754/fpcommon/normtopack.py | 15 +++++------ src/ieee754/fpcommon/pack.py | 14 +++++----- src/ieee754/fpcommon/postcalc.py | 5 ++-- src/ieee754/fpcommon/postnormalise.py | 14 +++++----- src/ieee754/fpcommon/roundz.py | 12 ++++----- src/ieee754/fpdiv/div0.py | 21 +++++++-------- src/ieee754/fpdiv/div1.py | 7 +++-- src/ieee754/fpdiv/div2.py | 13 +++++---- src/ieee754/fpdiv/divstages.py | 33 ++++++++++------------- src/ieee754/fpdiv/pipeline.py | 18 ++++++------- src/ieee754/fpdiv/specialcases.py | 26 +++++++++--------- src/ieee754/fpmul/mul0.py | 12 ++++----- src/ieee754/fpmul/mul1.py | 12 ++++----- src/ieee754/fpmul/mulstages.py | 11 ++++---- src/ieee754/fpmul/pipeline.py | 16 +++++------ src/ieee754/fpmul/specialcases.py | 23 ++++++++-------- 27 files changed, 207 insertions(+), 228 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 95b7f8d2..4e613f0d 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -79,12 +79,13 @@ class DivPipeBaseData: """ input data base type for ``DivPipe``. """ - def __init__(self, width, pspec): + def __init__(self, pspec): """ Create a ``DivPipeBaseData`` instance. """ + width = pspec['width'] self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc. + self.ctx = FPPipeContext(pspec) # context: muxid, operator etc. self.muxid = self.ctx.muxid # annoying. complicated. def __iter__(self): @@ -149,11 +150,11 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData): def __init__(self, core_config): """ Create a ``DivPipeInputData`` instance. """ DivPipeCoreInputData.__init__(self, core_config) - DivPipeBaseData.__init__(self, width, pspec) # XXX TODO args + DivPipeBaseData.__init__(self, pspec) # XXX TODO args self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc. + self.ctx = FPPipeContext(pspec) # context: muxid, operator etc. self.muxid = self.ctx.muxid # annoying. complicated. def __iter__(self): @@ -235,7 +236,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData): def __init__(self, core_config): """ Create a ``DivPipeCoreInterstageData`` instance. """ DivPipeCoreInterstageData.__init__(self, core_config) - DivPipeBaseData.__init__(self, width, pspec) # XXX TODO args + DivPipeBaseData.__init__(self, pspec) # XXX TODO args def __iter__(self): """ Get member signals. """ @@ -290,7 +291,7 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData): def __init__(self, core_config): """ Create a ``DivPipeCoreOutputData`` instance. """ DivPipeCoreOutputData.__init__(self, core_config) - DivPipeBaseData.__init__(self, width, pspec) # XXX TODO args + DivPipeBaseData.__init__(self, pspec) # XXX TODO args def __iter__(self): """ Get member signals. """ diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py index 7218be4e..c5c9dea9 100644 --- a/src/ieee754/fcvt/pipeline.py +++ b/src/ieee754/fcvt/pipeline.py @@ -37,19 +37,17 @@ class FPCVTSpecialCasesMod(Elaboratable): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, in_width, out_width, in_pspec, out_pspec): - self.in_width = in_width - self.out_width = out_width + def __init__(self, in_pspec, out_pspec): self.in_pspec = in_pspec self.out_pspec = out_pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPADDBaseData(self.in_width, self.in_pspec) + return FPADDBaseData(self.in_pspec) def ospec(self): - return FPAddStage1Data(self.out_width, self.out_pspec) + return FPAddStage1Data(self.out_pspec) def setup(self, m, i): """ links module to inputs and outputs @@ -66,8 +64,9 @@ class FPCVTSpecialCasesMod(Elaboratable): #m.submodules.sc_out_z = self.o.z # decode: XXX really should move to separate stage - print ("in_width out", self.in_width, self.out_width) - a1 = FPNumBaseRecord(self.in_width, False) + print ("in_width out", self.in_pspec['width'], + self.out_pspec['width']) + a1 = FPNumBaseRecord(self.in_pspec['width'], False) m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) m.d.comb += a1.v.eq(self.i.a) z1 = self.o.z @@ -158,19 +157,18 @@ class FPCVTSpecialCasesDeNorm(FPState, SimpleHandshake): """ special cases: NaNs, infs, zeros, denormalised """ - def __init__(self, in_width, out_width, in_pspec, out_pspec): + def __init__(self, in_pspec, out_pspec): FPState.__init__(self, "special_cases") - sc = FPCVTSpecialCasesMod(in_width, out_width, in_pspec, out_pspec) + sc = FPCVTSpecialCasesMod(in_pspec, out_pspec) SimpleHandshake.__init__(self, sc) self.out = self.ospec(None) class FPCVTBasePipe(ControlBase): - def __init__(self, in_width, out_width, in_pspec, out_pspec): + def __init__(self, in_pspec, out_pspec): ControlBase.__init__(self) - self.pipe1 = FPCVTSpecialCasesDeNorm(in_width, out_width, - in_pspec, out_pspec) - self.pipe2 = FPNormToPack(out_width, out_pspec) + self.pipe1 = FPCVTSpecialCasesDeNorm(in_pspec, out_pspec) + self.pipe2 = FPNormToPack(out_pspec) self._eqs = self.connect([self.pipe1, self.pipe2]) @@ -192,8 +190,6 @@ class FPCVTMuxInOut(ReservationStations): Fan-in and Fan-out are combinatorial. """ def __init__(self, in_width, out_width, num_rows, op_wid=0): - self.in_width = in_width - self.out_width = out_width self.op_wid = op_wid self.id_wid = num_bits(in_width) self.out_id_wid = num_bits(out_width) @@ -201,17 +197,18 @@ class FPCVTMuxInOut(ReservationStations): self.in_pspec = {} self.in_pspec['id_wid'] = self.id_wid self.in_pspec['op_wid'] = self.op_wid + self.in_pspec['width'] = self.in_width self.out_pspec = {} self.out_pspec['id_wid'] = self.out_id_wid - self.out_pspec['op_wid'] = self.op_wid + self.out_pspec['op_wid'] = op_wid + self.out_pspec['width'] = out_width - self.alu = FPCVTBasePipe(in_width, out_width, - self.in_pspec, self.out_pspec) + self.alu = FPCVTBasePipe(self.in_pspec, self.out_pspec) ReservationStations.__init__(self, num_rows) def i_specfn(self): - return FPADDBaseData(self.in_width, self.in_pspec) + return FPADDBaseData(self.in_pspec) def o_specfn(self): - return FPPackData(self.out_width, self.out_pspec) + return FPPackData(self.out_pspec) diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py index 5386f7d0..e5a683da 100644 --- a/src/ieee754/fpadd/add0.py +++ b/src/ieee754/fpadd/add0.py @@ -13,12 +13,13 @@ from ieee754.fpcommon.getop import FPPipeContext class FPAddStage0Data: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.z = FPNumBaseRecord(width, False) self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) self.tot = Signal(self.z.m_width + 4, reset_less=True) - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def eq(self, i): @@ -28,17 +29,16 @@ class FPAddStage0Data: class FPAddStage0Mod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, True) + return FPSCData(self.pspec, True) def ospec(self): - return FPAddStage0Data(self.width, self.pspec) + return FPAddStage0Data(self.pspec) def process(self, i): return self.o @@ -98,7 +98,7 @@ class FPAddStage0(FPState): give greatest accuracy. """ - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "add_0") self.mod = FPAddStage0Mod(width) self.o = self.mod.ospec() diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py index e434be21..70db8b47 100644 --- a/src/ieee754/fpadd/add1.py +++ b/src/ieee754/fpadd/add1.py @@ -16,17 +16,16 @@ class FPAddStage1Mod(FPState, Elaboratable): detects when tot sum is too big (tot[27] is kinda a carry bit) """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPAddStage0Data(self.width, self.pspec) + return FPAddStage0Data(self.pspec) def ospec(self): - return FPAddStage1Data(self.width, self.pspec) + return FPAddStage1Data(self.pspec) def process(self, i): return self.o @@ -72,7 +71,7 @@ class FPAddStage1Mod(FPState, Elaboratable): class FPAddStage1(FPState): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "add_1") self.mod = FPAddStage1Mod(width) self.out_z = FPNumBase(width, False) diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py index 45688c1c..d37828ee 100644 --- a/src/ieee754/fpadd/addstages.py +++ b/src/ieee754/fpadd/addstages.py @@ -18,27 +18,26 @@ from .add1 import FPAddStage1Mod class FPAddAlignSingleAdd(FPState, SimpleHandshake): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "align") - self.width = width self.pspec = pspec SimpleHandshake.__init__(self, self) # pipeline is its own stage self.a1o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, True) + return FPSCData(self.pspec, True) def ospec(self): - return FPAddStage1Data(self.width, self.pspec) # AddStage1 ospec + return FPAddStage1Data(self.pspec) # AddStage1 ospec def setup(self, m, i): """ links module to inputs and outputs """ # chain AddAlignSingle, AddStage0 and AddStage1 - mod = FPAddAlignSingleMod(self.width, self.pspec) - a0mod = FPAddStage0Mod(self.width, self.pspec) - a1mod = FPAddStage1Mod(self.width, self.pspec) + mod = FPAddAlignSingleMod(self.pspec) + a0mod = FPAddStage0Mod(self.pspec) + a1mod = FPAddStage1Mod(self.pspec) chain = StageChain([mod, a0mod, a1mod]) chain.setup(m, i) diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py index 70ce50b6..1db5affa 100644 --- a/src/ieee754/fpadd/align.py +++ b/src/ieee754/fpadd/align.py @@ -15,13 +15,14 @@ from ieee754.fpcommon.getop import FPPipeContext class FPNumIn2Ops: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.a = FPNumBaseRecord(width) self.b = FPNumBaseRecord(width) self.z = FPNumBaseRecord(width, False) self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def eq(self, i): @@ -74,9 +75,9 @@ class FPAddAlignMultiMod(FPState): class FPAddAlignMulti(FPState): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "align") - self.mod = FPAddAlignMultiMod(width, pspec) + self.mod = FPAddAlignMultiMod(pspec) self.out_a = FPNumBaseRecord(width) self.out_b = FPNumBaseRecord(width) self.exp_eq = Signal(reset_less=True) @@ -98,17 +99,16 @@ class FPAddAlignMulti(FPState): class FPAddAlignSingleMod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, True) + return FPSCData(self.pspec, True) def ospec(self): - return FPNumIn2Ops(self.width, self.pspec) + return FPNumIn2Ops(self.pspec) def process(self, i): return self.o @@ -136,8 +136,9 @@ class FPAddAlignSingleMod(Elaboratable): #m.submodules.align_out_b = self.o.b # temporary (muxed) input and output to be shifted - t_inp = FPNumBaseRecord(self.width) - t_out = FPNumBaseRecord(self.width) + width = self.pspec['width'] + t_inp = FPNumBaseRecord(width) + t_out = FPNumBaseRecord(width) espec = (len(self.i.a.e), True) msr = MultiShiftRMerge(self.i.a.m_width, espec) #m.submodules.align_t_in = t_inp @@ -193,9 +194,10 @@ class FPAddAlignSingleMod(Elaboratable): class FPAddAlignSingle(FPState): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "align") - self.mod = FPAddAlignSingleMod(width, pspec) + width = pspec['width'] + self.mod = FPAddAlignSingleMod(pspec) self.out_a = FPNumIn(None, width) self.out_b = FPNumIn(None, width) diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py index 7dbd254d..bee4cf3f 100644 --- a/src/ieee754/fpadd/pipeline.py +++ b/src/ieee754/fpadd/pipeline.py @@ -20,11 +20,11 @@ from .addstages import FPAddAlignSingleAdd class FPADDBasePipe(ControlBase): - def __init__(self, width, id_wid): + def __init__(self, pspec): ControlBase.__init__(self) - self.pipe1 = FPAddSpecialCasesDeNorm(width, id_wid) - self.pipe2 = FPAddAlignSingleAdd(width, id_wid) - self.pipe3 = FPNormToPack(width, id_wid) + self.pipe1 = FPAddSpecialCasesDeNorm(pspec) + self.pipe2 = FPAddAlignSingleAdd(pspec) + self.pipe3 = FPNormToPack(pspec) self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3]) @@ -47,15 +47,14 @@ class FPADDMuxInOut(ReservationStations): Fan-in and Fan-out are combinatorial. """ def __init__(self, width, num_rows, op_wid=None): - self.width = width self.id_wid = num_bits(width) self.op_wid = op_wid - self.pspec = {'id_wid': self.id_wid, 'op_wid': op_wid} - self.alu = FPADDBasePipe(width, self.pspec) + self.pspec = {'width': width, 'id_wid': self.id_wid, 'op_wid': op_wid} + self.alu = FPADDBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) def i_specfn(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def o_specfn(self): - return FPPackData(self.width, self.pspec) + return FPPackData(self.pspec) diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py index c0c8e24d..b6eb1a47 100644 --- a/src/ieee754/fpadd/specialcases.py +++ b/src/ieee754/fpadd/specialcases.py @@ -20,17 +20,16 @@ class FPAddSpecialCasesMod(Elaboratable): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def ospec(self): - return FPSCData(self.width, self.pspec, True) + return FPSCData(self.pspec, True) def setup(self, m, i): """ links module to inputs and outputs @@ -47,8 +46,9 @@ class FPAddSpecialCasesMod(Elaboratable): #m.submodules.sc_out_z = self.o.z # decode: XXX really should move to separate stage - a1 = FPNumBaseRecord(self.width) - b1 = FPNumBaseRecord(self.width) + width = self.pspec['width'] + a1 = FPNumBaseRecord(width) + b1 = FPNumBaseRecord(width) m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1) m.d.comb += [a1.v.eq(self.i.a), @@ -182,24 +182,23 @@ class FPAddSpecialCasesDeNorm(FPState, SimpleHandshake): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "special_cases") - self.width = width self.pspec = pspec SimpleHandshake.__init__(self, self) # pipe is its own stage self.out = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) # SC ispec + return FPADDBaseData(self.pspec) # SC ispec def ospec(self): - return FPSCData(self.width, self.pspec, True) # DeNorm + return FPSCData(self.pspec, True) # DeNorm def setup(self, m, i): """ links module to inputs and outputs """ - smod = FPAddSpecialCasesMod(self.width, self.pspec) - dmod = FPAddDeNormMod(self.width, self.pspec, True) + smod = FPAddSpecialCasesMod(self.pspec) + dmod = FPAddDeNormMod(self.pspec, True) chain = StageChain([smod, dmod]) chain.setup(m, i) diff --git a/src/ieee754/fpcommon/corrections.py b/src/ieee754/fpcommon/corrections.py index 50079226..18a08a04 100644 --- a/src/ieee754/fpcommon/corrections.py +++ b/src/ieee754/fpcommon/corrections.py @@ -10,17 +10,16 @@ from .roundz import FPRoundData class FPCorrectionsMod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.out_z = self.ospec() def ispec(self): - return FPRoundData(self.width, self.pspec) + return FPRoundData(self.pspec) def ospec(self): - return FPRoundData(self.width, self.pspec) + return FPRoundData(self.pspec) def process(self, i): return self.out_z diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py index 6c2ed584..58621369 100644 --- a/src/ieee754/fpcommon/denorm.py +++ b/src/ieee754/fpcommon/denorm.py @@ -13,18 +13,18 @@ from ieee754.fpcommon.getop import FPPipeContext class FPSCData: - def __init__(self, width, pspec, m_extra): - + def __init__(self, pspec, m_extra): + width = pspec['width'] # NOTE: difference between z and oz is that oz is created by # special-cases module(s) and will propagate, along with its # "bypass" signal out_do_z, through the pipeline, *disabling* # all processing of all subsequent stages. self.a = FPNumBaseRecord(width, m_extra) # operand a self.b = FPNumBaseRecord(width, m_extra) # operand b - self.z = FPNumBaseRecord(width, False) # denormed result + self.z = FPNumBaseRecord(width, False) # denormed result self.oz = Signal(width, reset_less=True) # "finished" (bypass) result self.out_do_z = Signal(reset_less=True) # "bypass" enabled - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def __iter__(self): @@ -43,18 +43,17 @@ class FPSCData: class FPAddDeNormMod(FPState, Elaboratable): - def __init__(self, width, pspec, m_extra): - self.width = width + def __init__(self, pspec, m_extra): self.pspec = pspec self.m_extra = m_extra self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, self.m_extra) + return FPSCData(self.pspec, self.m_extra) def ospec(self): - return FPSCData(self.width, self.pspec, self.m_extra) + return FPSCData(self.pspec, self.m_extra) def process(self, i): return self.o diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py index abe7dc94..fbdee3e8 100644 --- a/src/ieee754/fpcommon/getop.py +++ b/src/ieee754/fpcommon/getop.py @@ -84,8 +84,7 @@ class FPNumBase2Ops: class FPPipeContext: - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): print (pspec) self.id_wid = pspec['id_wid'] self.op_wid = pspec.get('op_wid', 0) @@ -107,9 +106,9 @@ class FPPipeContext: class FPADDBaseData: - def __init__(self, width, pspec, n_ops=2): - self.width = width - self.ctx = FPPipeContext(width, pspec) + def __init__(self, pspec, n_ops=2): + width = pspec['width'] + self.ctx = FPPipeContext(pspec) ops = [] for i in range(n_ops): name = chr(ord("a")+i) diff --git a/src/ieee754/fpcommon/normtopack.py b/src/ieee754/fpcommon/normtopack.py index 1cda8765..cb4a8bcd 100644 --- a/src/ieee754/fpcommon/normtopack.py +++ b/src/ieee754/fpcommon/normtopack.py @@ -16,28 +16,27 @@ from .pack import FPPackData, FPPackMod class FPNormToPack(FPState, SimpleHandshake): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "normalise_1") print ("normtopack", pspec) self.pspec = pspec - self.width = width SimpleHandshake.__init__(self, self) # pipeline is its own stage def ispec(self): - return FPAddStage1Data(self.width, self.pspec) + return FPAddStage1Data(self.pspec) def ospec(self): - return FPPackData(self.width, self.pspec) # FPPackMod + return FPPackData(self.pspec) # FPPackMod def setup(self, m, i): """ links module to inputs and outputs """ # Normalisation, Rounding Corrections, Pack - in a chain - nmod = FPNorm1ModSingle(self.width, self.pspec) - rmod = FPRoundMod(self.width, self.pspec) - cmod = FPCorrectionsMod(self.width, self.pspec) - pmod = FPPackMod(self.width, self.pspec) + nmod = FPNorm1ModSingle(self.pspec) + rmod = FPRoundMod(self.pspec) + cmod = FPCorrectionsMod(self.pspec) + pmod = FPPackMod(self.pspec) stages = [nmod, rmod, cmod, pmod] chain = StageChain(stages) chain.setup(m, i) diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py index eae7c6b7..529dd51b 100644 --- a/src/ieee754/fpcommon/pack.py +++ b/src/ieee754/fpcommon/pack.py @@ -14,9 +14,10 @@ from ieee754.fpcommon.getop import FPPipeContext class FPPackData: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.z = Signal(width, reset_less=True) # result - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) # this is complicated: it's a workaround, due to the # array-indexing not working properly in nmigen. @@ -40,17 +41,16 @@ class FPPackData: class FPPackMod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPRoundData(self.width, self.pspec) + return FPRoundData(self.pspec) def ospec(self): - return FPPackData(self.width, self.pspec) + return FPPackData(self.pspec) def process(self, i): return self.o @@ -63,7 +63,7 @@ class FPPackMod(Elaboratable): def elaborate(self, platform): m = Module() - z = FPNumBaseRecord(self.width, False) + z = FPNumBaseRecord(self.pspec['width'], False) m.submodules.pack_in_z = in_z = FPNumBase(self.i.z) #m.submodules.pack_out_z = out_z = FPNumOut(z) m.d.comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/ieee754/fpcommon/postcalc.py b/src/ieee754/fpcommon/postcalc.py index a06c99a8..c8a0090e 100644 --- a/src/ieee754/fpcommon/postcalc.py +++ b/src/ieee754/fpcommon/postcalc.py @@ -8,12 +8,13 @@ from ieee754.fpcommon.getop import FPPipeContext class FPAddStage1Data: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.z = FPNumBaseRecord(width, False) self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) self.of = Overflow() - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def __iter__(self): diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py index 95e49174..58ce1e66 100644 --- a/src/ieee754/fpcommon/postnormalise.py +++ b/src/ieee754/fpcommon/postnormalise.py @@ -16,12 +16,13 @@ from .postcalc import FPAddStage1Data class FPNorm1Data: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.roundz = Signal(reset_less=True, name="norm1_roundz") self.z = FPNumBaseRecord(width, False) self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def eq(self, i): @@ -32,17 +33,16 @@ class FPNorm1Data: class FPNorm1ModSingle(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPAddStage1Data(self.width, self.pspec) + return FPAddStage1Data(self.pspec) def ospec(self): - return FPNorm1Data(self.width, self.pspec) + return FPNorm1Data(self.pspec) def setup(self, m, i): """ links module to inputs and outputs @@ -140,7 +140,7 @@ class FPNorm1ModSingle(Elaboratable): class FPNorm1ModMulti: - def __init__(self, width, single_cycle=True): + def __init__(self, pspec, single_cycle=True): self.width = width self.in_select = Signal(reset_less=True) self.in_z = FPNumBase(width, False) diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py index 3aa8bf4a..1585b310 100644 --- a/src/ieee754/fpcommon/roundz.py +++ b/src/ieee754/fpcommon/roundz.py @@ -13,9 +13,10 @@ from .postnormalise import FPNorm1Data class FPRoundData: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.z = FPNumBaseRecord(width, False) - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid # pipeline bypass [data comes from specialcases] self.out_do_z = Signal(reset_less=True) @@ -29,17 +30,16 @@ class FPRoundData: class FPRoundMod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.out_z = self.ospec() def ispec(self): - return FPNorm1Data(self.width, self.pspec) + return FPNorm1Data(self.pspec) def ospec(self): - return FPRoundData(self.width, self.pspec) + return FPRoundData(self.pspec) def process(self, i): return self.out_z diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index fb2bccd6..81166c74 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -15,12 +15,12 @@ from ieee754.fpcommon.getop import FPPipeContext # TODO: delete (replace by DivPipeCoreInputData) class FPDivStage0Data: - def __init__(self, width, pspec): - self.z = FPNumBaseRecord(width, False) + def __init__(self, pspec): + self.z = FPNumBaseRecord(pspec['width'], False) self.out_do_z = Signal(reset_less=True) - self.oz = Signal(width, reset_less=True) + self.oz = Signal(pspec['width'], reset_less=True) - self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc. + self.ctx = FPPipeContext(pspec['width'], pspec) # context: muxid, operator etc. self.muxid = self.ctx.muxid # annoying. complicated. # TODO: here is where Q and R would be put, and passed @@ -36,18 +36,17 @@ class FPDivStage0Data: class FPDivStage0Mod(Elaboratable): - def __init__(self, width, id_wid): - self.width = width - self.id_wid = id_wid + def __init__(self, pspec): + self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPSCData(self.width, self.id_wid, False) + return FPSCData(self.pspec, False) def ospec(self): # XXX TODO: replace with DivPipeCoreInputData, here - return FPDivStage0Data(self.width, self.id_wid) + return FPDivStage0Data(self.pspec) def process(self, i): return self.o @@ -105,9 +104,9 @@ class FPDivStage0(FPState): """ First stage of div. """ - def __init__(self, width, id_wid): + def __init__(self, pspec): FPState.__init__(self, "divider_0") - self.mod = FPDivStage0Mod(width) + self.mod = FPDivStage0Mod(pspec) self.o = self.mod.ospec() def setup(self, m, i): diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py index 27e4b782..6cf49aba 100644 --- a/src/ieee754/fpdiv/div1.py +++ b/src/ieee754/fpdiv/div1.py @@ -14,19 +14,18 @@ from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData class FPDivStage1Mod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): # TODO: DivPipeCoreInterstageData, here - return FPDivStage0Data(self.width, self.pspec) # Q/Rem (etc) in... + return FPDivStage0Data(self.pspec) # Q/Rem (etc) in... def ospec(self): # TODO: DivPipeCoreInterstageData, here - return FPDivStage0Data(self.width, self.pspec) # ... Q/Rem (etc) out + return FPDivStage0Data(self.pspec) # ... Q/Rem (etc) out def process(self, i): return self.o diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py index 43153fc9..8db281ae 100644 --- a/src/ieee754/fpdiv/div2.py +++ b/src/ieee754/fpdiv/div2.py @@ -15,20 +15,19 @@ class FPDivStage2Mod(FPState, Elaboratable): """ Second stage of div: preparation for normalisation. """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): # TODO: DivPipeCoreInterstageData - return FPDivStage0Data(self.width, self.pspec) # Q/Rem in... + return FPDivStage0Data(self.pspec) # Q/Rem in... def ospec(self): # XXX REQUIRED. MUST NOT BE CHANGED. this is the format # required for ongoing processing (normalisation, correction etc.) - return FPAddStage1Data(self.width, self.pspec) # out to post-process + return FPAddStage1Data(self.pspec) # out to post-process def process(self, i): return self.o @@ -75,10 +74,10 @@ class FPDivStage2Mod(FPState, Elaboratable): class FPDivStage2(FPState): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "divider_1") - self.mod = FPDivStage2Mod(width) - self.out_z = FPNumBaseRecord(width, False) + self.mod = FPDivStage2Mod(pspec) + self.out_z = FPNumBaseRecord(pspec, False) self.out_of = Overflow() self.norm_stb = Signal() diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py index b0c539f9..c5f76834 100644 --- a/src/ieee754/fpdiv/divstages.py +++ b/src/ieee754/fpdiv/divstages.py @@ -25,9 +25,8 @@ from .div0 import FPDivStage0Data class FPDivStagesSetup(FPState, SimpleHandshake): - def __init__(self, width, pspec, n_stages): + def __init__(self, pspec, n_stages): FPState.__init__(self, "divsetup") - self.width = width self.pspec = pspec self.n_stages = n_stages # number of combinatorial stages SimpleHandshake.__init__(self, self) # pipeline is its own stage @@ -35,11 +34,11 @@ class FPDivStagesSetup(FPState, SimpleHandshake): def ispec(self): # REQUIRED. do NOT change. - return FPSCData(self.width, self.pspec, False) # from denorm + return FPSCData(self.pspec, False) # from denorm def ospec(self): # XXX TODO: replace with "intermediary" (DivPipeInterstageData) - return FPDivStage0Data(self.width, self.pspec) # DIV ospec (loop) + return FPDivStage0Data(self.pspec) # DIV ospec (loop) def setup(self, m, i): """ links module to inputs and outputs. @@ -53,7 +52,7 @@ class FPDivStagesSetup(FPState, SimpleHandshake): divstages = [] # Converts from FPSCData into DivPipeInputData - divstages.append(FPDivStage0Mod(self.width, self.pspec)) + divstages.append(FPDivStage0Mod(self.pspec)) # does 1 "convert" (actual processing) from DivPipeInputData # into "intermediate" output (DivPipeInterstageData) @@ -67,7 +66,7 @@ class FPDivStagesSetup(FPState, SimpleHandshake): # will add. for count in range(self.n_stages): # number of combinatorial stages # XXX: this can actually be entirely dropped... - divstages.append(FPDivStage1Mod(self.width, self.pspec)) + divstages.append(FPDivStage1Mod(self.pspec)) # ... and replaced with this. # vvvvvvv @@ -90,25 +89,22 @@ class FPDivStagesSetup(FPState, SimpleHandshake): class FPDivStagesIntermediary(FPState, SimpleHandshake): - def __init__(self, width, pspec, n_stages): + def __init__(self, pspec, n_stages): FPState.__init__(self, "divintermediate") - self.width = width self.pspec = pspec self.n_stages = n_stages # number of combinatorial stages - self.begin = begin # "begin" mode - self.end = end # "end" mode SimpleHandshake.__init__(self, self) # pipeline is its own stage self.m1o = self.ospec() def ispec(self): # TODO - this is for FPDivStage1Mod # XXX TODO: replace with "intermediary" (DivPipeInterstageData) - return FPDivStage0Data(self.width, self.pspec) # DIV ispec (loop) + return FPDivStage0Data(self.pspec) # DIV ispec (loop) def ospec(self): # TODO - this is for FPDivStage1Mod # XXX TODO: replace with "intermediary" (DivPipeInterstageData) - return FPDivStage0Data(self.width, self.pspec) # DIV ospec (loop) + return FPDivStage0Data(self.pspec) # DIV ospec (loop) def setup(self, m, i): """ links module to inputs and outputs. @@ -126,7 +122,7 @@ class FPDivStagesIntermediary(FPState, SimpleHandshake): # will add. for count in range(self.n_stages): # number of combinatorial stages # XXX: this can actually be entirely dropped... - divstages.append(FPDivStage1Mod(self.width, self.pspec)) + divstages.append(FPDivStage1Mod(self.pspec)) # ... and replaced with this. # vvvvvvv @@ -149,9 +145,8 @@ class FPDivStagesIntermediary(FPState, SimpleHandshake): class FPDivStagesFinal(FPState, SimpleHandshake): - def __init__(self, width, pspec, n_stages): + def __init__(self, pspec, n_stages): FPState.__init__(self, "divfinal") - self.width = width self.pspec = pspec self.n_stages = n_stages # number of combinatorial stages SimpleHandshake.__init__(self, self) # pipeline is its own stage @@ -159,11 +154,11 @@ class FPDivStagesFinal(FPState, SimpleHandshake): def ispec(self): # XXX TODO: replace with "intermediary" (DivPipeInterstageData?) - return FPDivStage0Data(self.width, self.pspec) # DIV ispec (loop) + return FPDivStage0Data(self.pspec) # DIV ispec (loop) def ospec(self): # REQUIRED. do NOT change. - return FPAddStage1Data(self.width, self.pspec) # to post-norm + return FPAddStage1Data(self.pspec) # to post-norm def setup(self, m, i): """ links module to inputs and outputs. @@ -184,7 +179,7 @@ class FPDivStagesFinal(FPState, SimpleHandshake): # will add. for count in range(self.n_stages): # number of combinatorial stages # XXX: this can actually be entirely dropped... - divstages.append(FPDivStage1Mod(self.width, self.pspec)) + divstages.append(FPDivStage1Mod(self.pspec)) # ... and replaced with this. # vvvvvvv @@ -199,7 +194,7 @@ class FPDivStagesFinal(FPState, SimpleHandshake): # does conversion from DivPipeOutputData into # FPAddStage1Data format (bad name, TODO, doesn't matter), # so that post-normalisation and corrections can take over - divstages.append(FPDivStage2Mod(self.width, self.pspec)) + divstages.append(FPDivStage2Mod(self.pspec)) chain = StageChain(divstages) chain.setup(m, i) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 21f746ba..58fa8e9b 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -73,9 +73,8 @@ from .divstages import (FPDivStagesSetup, class FPDIVBasePipe(ControlBase): - def __init__(self, width, pspec): + def __init__(self, pspec): ControlBase.__init__(self) - self.width = width self.pspec = pspec def elaborate(self, platform): @@ -104,11 +103,11 @@ class FPDIVBasePipe(ControlBase): else: kls = FPDivStagesIntermediate - pipechain.append(kls(self.width, self.pspec, n_comb_stages)) + pipechain.append(kls(self.pspec, n_comb_stages)) # start and end: unpack/specialcases then normalisation/packing - pipestart = FPDIVSpecialCasesDeNorm(self.width, self.pspec) - pipeend = FPNormToPack(self.width, self.pspec) + pipestart = FPDIVSpecialCasesDeNorm(self.pspec) + pipeend = FPNormToPack(self.pspec) # add submodules m.submodules.scnorm = pipestart @@ -135,14 +134,13 @@ class FPDIVMuxInOut(ReservationStations): then be used to change the behaviour of the pipeline. """ def __init__(self, width, num_rows, op_wid=0): - self.width = width self.id_wid = num_bits(width) - self.pspec = {'id_wid': self.id_wid, 'op_wid': op_wid} - self.alu = FPDIVBasePipe(width, self.pspec) + self.pspec = {'width': width, 'id_wid': self.id_wid, 'op_wid': op_wid} + self.alu = FPDIVBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) def i_specfn(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def o_specfn(self): - return FPPackData(self.width, self.pspec) + return FPPackData(self.pspec) diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py index b7a05047..f1704424 100644 --- a/src/ieee754/fpdiv/specialcases.py +++ b/src/ieee754/fpdiv/specialcases.py @@ -18,17 +18,16 @@ class FPDIVSpecialCasesMod(Elaboratable): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def ospec(self): - return FPSCData(self.width, self.pspec, False) + return FPSCData(self.pspec, False) def setup(self, m, i): """ links module to inputs and outputs @@ -45,8 +44,8 @@ class FPDIVSpecialCasesMod(Elaboratable): #m.submodules.sc_out_z = self.o.z # decode: XXX really should move to separate stage - a1 = FPNumBaseRecord(self.width, False) - b1 = FPNumBaseRecord(self.width, False) + a1 = FPNumBaseRecord(self.pspec['width'], False) + b1 = FPNumBaseRecord(self.pspec['width'], False) m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1) m.d.comb += [a1.v.eq(self.i.a), @@ -113,9 +112,9 @@ class FPDIVSpecialCases(FPState): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "special_cases") - self.mod = FPDIVSpecialCasesMod(width) + self.mod = FPDIVSpecialCasesMod(pspec) self.out_z = self.mod.ospec() self.out_do_z = Signal(reset_less=True) @@ -138,24 +137,23 @@ class FPDIVSpecialCasesDeNorm(FPState, SimpleHandshake): """ special cases: NaNs, infs, zeros, denormalised """ - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "special_cases") - self.width = width self.pspec = pspec SimpleHandshake.__init__(self, self) # pipe is its own stage self.out = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) # SpecialCases ispec + return FPADDBaseData(self.pspec) # SpecialCases ispec def ospec(self): - return FPSCData(self.width, self.pspec, False) # DeNorm ospec + return FPSCData(self.pspec, False) # DeNorm ospec def setup(self, m, i): """ links module to inputs and outputs """ - smod = FPDIVSpecialCasesMod(self.width, self.pspec) - dmod = FPAddDeNormMod(self.width, self.pspec, False) + smod = FPDIVSpecialCasesMod(self.pspec) + dmod = FPAddDeNormMod(self.pspec, False) chain = StageChain([smod, dmod]) chain.setup(m, i) diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py index db89b336..f56f69b5 100644 --- a/src/ieee754/fpmul/mul0.py +++ b/src/ieee754/fpmul/mul0.py @@ -13,13 +13,14 @@ from ieee754.fpcommon.getop import FPPipeContext class FPMulStage0Data: - def __init__(self, width, pspec): + def __init__(self, pspec): + width = pspec['width'] self.z = FPNumBaseRecord(width, False) self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1 self.product = Signal(mw, reset_less=True) - self.ctx = FPPipeContext(width, pspec) + self.ctx = FPPipeContext(pspec) self.muxid = self.ctx.muxid def eq(self, i): @@ -29,17 +30,16 @@ class FPMulStage0Data: class FPMulStage0Mod(Elaboratable): - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, False) + return FPSCData(self.pspec, False) def ospec(self): - return FPMulStage0Data(self.width, self.pspec) + return FPMulStage0Data(self.pspec) def process(self, i): return self.o diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py index e6e58fc4..1611fe18 100644 --- a/src/ieee754/fpmul/mul1.py +++ b/src/ieee754/fpmul/mul1.py @@ -12,17 +12,16 @@ class FPMulStage1Mod(FPState, Elaboratable): """ Second stage of mul: preparation for normalisation. """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPMulStage0Data(self.width, self.pspec) + return FPMulStage0Data(self.pspec) def ospec(self): - return FPAddStage1Data(self.width, self.pspec) + return FPAddStage1Data(self.pspec) def process(self, i): return self.o @@ -57,9 +56,10 @@ class FPMulStage1Mod(FPState, Elaboratable): class FPMulStage1(FPState): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "multiply_1") - self.mod = FPMulStage1Mod(width, pspec) + width = pspec['width'] + self.mod = FPMulStage1Mod(pspec) self.out_z = FPNumBaseRecord(width, False) self.out_of = Overflow() self.norm_stb = Signal() diff --git a/src/ieee754/fpmul/mulstages.py b/src/ieee754/fpmul/mulstages.py index 53f4cc7f..fbfe8c7c 100644 --- a/src/ieee754/fpmul/mulstages.py +++ b/src/ieee754/fpmul/mulstages.py @@ -14,26 +14,25 @@ from .mul1 import FPMulStage1Mod class FPMulStages(FPState, SimpleHandshake): - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "align") - self.width = width self.pspec = pspec SimpleHandshake.__init__(self, self) # pipeline is its own stage self.m1o = self.ospec() def ispec(self): - return FPSCData(self.width, self.pspec, False) + return FPSCData(self.pspec, False) def ospec(self): - return FPAddStage1Data(self.width, self.pspec) + return FPAddStage1Data(self.pspec) def setup(self, m, i): """ links module to inputs and outputs """ # chain MulStage0 and MulStage1 - m0mod = FPMulStage0Mod(self.width, self.pspec) - m1mod = FPMulStage1Mod(self.width, self.pspec) + m0mod = FPMulStage0Mod(self.pspec) + m1mod = FPMulStage1Mod(self.pspec) chain = StageChain([m0mod, m1mod]) chain.setup(m, i) diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py index d735211c..f146b1a7 100644 --- a/src/ieee754/fpmul/pipeline.py +++ b/src/ieee754/fpmul/pipeline.py @@ -18,11 +18,11 @@ from .mulstages import FPMulStages class FPMULBasePipe(ControlBase): - def __init__(self, width, pspec): + def __init__(self, pspec): ControlBase.__init__(self) - self.pipe1 = FPMulSpecialCasesDeNorm(width, pspec) - self.pipe2 = FPMulStages(width, pspec) - self.pipe3 = FPNormToPack(width, pspec) + self.pipe1 = FPMulSpecialCasesDeNorm(pspec) + self.pipe2 = FPMulStages(pspec) + self.pipe3 = FPNormToPack(pspec) self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3]) @@ -45,17 +45,17 @@ class FPMULMuxInOut(ReservationStations): Fan-in and Fan-out are combinatorial. """ def __init__(self, width, num_rows, op_wid=0): - self.width = width self.pspec = {} self.id_wid = num_bits(width) self.op_wid = op_wid self.pspec['id_wid'] = self.id_wid + self.pspec['width'] = width self.pspec['op_wid'] = self.op_wid - self.alu = FPMULBasePipe(width, self.pspec) + self.alu = FPMULBasePipe(self.pspec) ReservationStations.__init__(self, num_rows) def i_specfn(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def o_specfn(self): - return FPPackData(self.width, self.pspec) + return FPPackData(self.pspec) diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py index dab89b27..c84eed71 100644 --- a/src/ieee754/fpmul/specialcases.py +++ b/src/ieee754/fpmul/specialcases.py @@ -18,17 +18,16 @@ class FPMulSpecialCasesMod(Elaboratable): https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, pspec): - self.width = width + def __init__(self, pspec): self.pspec = pspec self.i = self.ispec() self.o = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def ospec(self): - return FPSCData(self.width, self.pspec, False) + return FPSCData(self.pspec, False) def setup(self, m, i): """ links module to inputs and outputs @@ -45,8 +44,9 @@ class FPMulSpecialCasesMod(Elaboratable): #m.submodules.sc_out_z = self.o.z # decode: XXX really should move to separate stage - a1 = FPNumBaseRecord(self.width, False) - b1 = FPNumBaseRecord(self.width, False) + width = self.pspec['width'] + a1 = FPNumBaseRecord(width, False) + b1 = FPNumBaseRecord(width, False) m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1) m.d.comb += [a1.v.eq(self.i.a), @@ -131,24 +131,23 @@ class FPMulSpecialCasesDeNorm(FPState, SimpleHandshake): """ special cases: NaNs, infs, zeros, denormalised """ - def __init__(self, width, pspec): + def __init__(self, pspec): FPState.__init__(self, "special_cases") - self.width = width self.pspec = pspec SimpleHandshake.__init__(self, self) # pipe is its own stage self.out = self.ospec() def ispec(self): - return FPADDBaseData(self.width, self.pspec) + return FPADDBaseData(self.pspec) def ospec(self): - return FPSCData(self.width, self.pspec, False) + return FPSCData(self.pspec, False) def setup(self, m, i): """ links module to inputs and outputs """ - smod = FPMulSpecialCasesMod(self.width, self.pspec) - dmod = FPAddDeNormMod(self.width, self.pspec, False) + smod = FPMulSpecialCasesMod(self.pspec) + dmod = FPAddDeNormMod(self.pspec, False) chain = StageChain([smod, dmod]) chain.setup(m, i) -- 2.30.2