From bae0f14b5bcbc05f3644957dbe310be9ad253d14 Mon Sep 17 00:00:00 2001 From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0" Date: Tue, 23 Jun 2020 22:43:41 +0100 Subject: [PATCH] --- cole.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cole.mdwn b/cole.mdwn index daf4019bb..9addee630 100644 --- a/cole.mdwn +++ b/cole.mdwn @@ -7,10 +7,11 @@ List of things that need more fleshed out bug reports: * Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG +* Memory bus/L1/L2 Cache documentation (bug #397) * Bperm tutorial * Bugseverywhere (or also https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go) * Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html) -* Memory bus/L1/L2 Cache documentation (bug #397) + * Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html) * LDST documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html) * Follow up with graphics engineers, esp ones Yehowshua has already reached out to (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008283.html) -- 2.30.2