From bb100f0b7583d8bbffded190b3576385658e0ee1 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Apr 2022 13:52:32 +0100
Subject: [PATCH] whoops should be in openpower-isa (as an overlay)

---
 openpower/isa/svfixedarith.mdwn | 47 ---------------------------------
 openpower/sv/biginteger.mdwn    | 21 ++++++++-------
 2 files changed, 12 insertions(+), 56 deletions(-)
 delete mode 100644 openpower/isa/svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
deleted file mode 100644
index ebef59cea..000000000
--- a/openpower/isa/svfixedarith.mdwn
+++ /dev/null
@@ -1,47 +0,0 @@
-# [DRAFT] Twin Multiply and Add Doubleword
-
-VA-Form
-
-* madded RT,RA,RB,RC
-
-Pseudo-code:
-
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
-    prod[0:127] <- (RA) * (RB)
-    sum[0:127] <- EXTZ(RC) + prod
-    RT <- sum[64:127]
-    RS <- sum[0:63]
-
-Special Registers Altered:
-
-    None
-
-# [DRAFT] Twin Divide Quad Unsigned
-
-VA-Form
-
-* divmod2du   RT,RA,RB,RC
-
-Pseudo-code:
-
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
-    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
-        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
-        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
-        result <- dividend / divisor
-        modulo <- dividend % divisor
-        RT <- result[XLEN:(XLEN*2)-1]
-        RS <- modulo[XLEN:(XLEN*2)-1]
-        overflow <- 0
-    else
-        overflow <- 1
-        RT <- [1]*XLEN
-        RS <- [0]*XLEN
-
-Special Registers Altered:
-
-    None
diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 44f67f85d..1d15f0965 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -82,15 +82,6 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical
 to RC extended to SVP64 numbering, including whether RC is set Scalar or
 Vector.
 
-For the Opcode map (XO Field)
-see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
-Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) which is
-in `110010`.
-
-| 110000 | 110001  | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 |
-| ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ |
-| maddhd | maddhdu | madded | maddld | rsvd   | rsvd   | rsvd   | rsvd   |
-
 # divqdu RT,EA,RB
 
 Divide Quad-Double Extended Unsigned is an XO-Form instruction
@@ -102,3 +93,15 @@ division, producing a 64 bit result.
 Pseudo-code:
 
     dividend[0:(XLEN*2)-1] <- (RA) || (RS)
+
+# [DRAFT] EXT04 Proposed Map
+
+For the Opcode map (XO Field)
+see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
+Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) in `110010`
+and `divrem2du` in `110100`
+
+|110000|110001 |110010    |110011|110100       |110101|110110|110111|
+|------|-------|----------|------|-------------|------|------|------|
+|maddhd|maddhdu|**madded**|maddld|**divrem2du**|rsvd  |rsvd  |rsvd  |
+
-- 
2.30.2