From bb16e1067261779414e2f64ada14b0d4d0a9a0f4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Feb 2022 14:27:52 +0000 Subject: [PATCH] add fpga/top-ulx3s.vhdl which sets dummy values for verilator signals this stops a whole batch of unnecessary debug signals going into the nextpnr-ecp5 LPF constraints --- Makefile | 9 ++-- fpga/top-ulx3s.vhdl | 126 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 131 insertions(+), 4 deletions(-) create mode 100644 fpga/top-ulx3s.vhdl diff --git a/Makefile b/Makefile index f4dc54d..8af9442 100644 --- a/Makefile +++ b/Makefile @@ -156,6 +156,10 @@ SIM_BRAM_CHAINBOOT=6291456 # 0x600000 FPGA_TARGET ?= ORANGE-CRAB +clkgen=fpga/clk_gen_ecp5.vhd +toplevel=fpga/top-generic.vhdl +dmi_dtm=dmi_dtm_dummy.vhdl + # ULX3S with ECP85 ifeq ($(FPGA_TARGET), ULX3S) RESET_LOW=true @@ -166,6 +170,7 @@ PACKAGE=CABGA381 NEXTPNR_FLAGS=--85k --freq 25 OPENOCD_JTAG_CONFIG=openocd/ulx3s.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg +toplevel=fpga/top-ulx3s.vhdl endif # OrangeCrab with ECP85 @@ -194,10 +199,6 @@ endif -clkgen=fpga/clk_gen_ecp5.vhd -toplevel=fpga/top-generic.vhdl -dmi_dtm=dmi_dtm_dummy.vhdl - ifeq ($(FPGA_TARGET), verilator) RESET_LOW=true CLK_INPUT=50000000 diff --git a/fpga/top-ulx3s.vhdl b/fpga/top-ulx3s.vhdl new file mode 100644 index 0000000..ceecd43 --- /dev/null +++ b/fpga/top-ulx3s.vhdl @@ -0,0 +1,126 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity toplevel is + generic ( + MEMORY_SIZE : positive := (384*1024); + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + PLL_RESET_BITS : positive := 18; + EXTERNAL_CORE : boolean := false; + SIM_MAIN_BRAM : boolean := false; + SIM_BRAM_CHAINBOOT : positive := 0; + CLK_INPUT : positive := 100000000; + CLK_FREQUENCY : positive := 100000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := false; + LOG_LENGTH : natural := 512; + DISABLE_FLATTEN_CORE : boolean := false; + UART_IS_16550 : boolean := true; + HAS_UART1 : boolean := false + ); + port( + ext_clk : in std_ulogic; + ext_rst : in std_ulogic; + + -- UART0 signals: + uart0_txd : out std_ulogic; + uart0_rxd : in std_ulogic + ); +end entity toplevel; + +architecture behaviour of toplevel is + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + + -- BRAM verilator access + signal no_bram_we : std_ulogic; + signal no_bram_re : std_ulogic; + signal no_bram_addr : std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); + signal no_bram_di : std_logic_vector(63 downto 0); + signal no_bram_do : std_logic_vector(63 downto 0); + signal no_bram_sel : std_logic_vector(7 downto 0); + + -- for verilator debugging + signal no_nia_req: std_ulogic; + signal no_nia: std_ulogic_vector(63 downto 0); + signal no_msr_o: std_ulogic_vector(63 downto 0); + signal no_insn: std_ulogic_vector(31 downto 0); + signal no_ldst_req: std_ulogic; + signal no_ldst_addr: std_ulogic_vector(63 downto 0); + +begin + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => PLL_RESET_BITS + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => CLK_INPUT, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => MEMORY_SIZE, + SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT, + SIM_MAIN_BRAM => SIM_MAIN_BRAM, + EXTERNAL_CORE => EXTERNAL_CORE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + LOG_LENGTH => LOG_LENGTH, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1 + ) + port map ( + system_clk => system_clk, + rst => soc_rst, + uart0_txd => uart0_txd, + uart0_rxd => uart0_rxd, + bram_we => no_bram_we, + bram_re => no_bram_re, + bram_addr => no_bram_addr, + bram_di => no_bram_di, + bram_do => no_bram_do, + bram_sel => no_bram_sel, + nia_req => no_nia_req, + nia => no_nia, + msr_o => no_msr_o, + insn => no_insn, + ldst_req => no_ldst_req, + ldst_addr => no_ldst_addr + ); + +end architecture behaviour; -- 2.30.2