From bb22bd7d9ec6a874d1b8797ed81a4763dee3b917 Mon Sep 17 00:00:00 2001
From: Chris Demetriou <cgd@google.com>
Date: Fri, 1 Mar 2002 07:34:57 +0000
Subject: [PATCH] 2002-02-28  Chris Demetriou  <cgd@broadcom.com>

        * mips.igen (DSRA32, DSRAV): Fix order of arguments in
        instruction-printing string.
        (LWU): Use '64' as the filter flag.
---
 sim/mips/ChangeLog | 6 ++++++
 sim/mips/mips.igen | 6 +++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index e3ca0ec04ac..cb69ddb74c2 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,9 @@
+2002-02-28  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.igen (DSRA32, DSRAV): Fix order of arguments in
+	instruction-printing string.
+	(LWU): Use '64' as the filter flag.
+
 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 
 	* mips.igen (SDXC1): Fix instruction-printing string.
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index eb511194591..02ae7607835 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1248,7 +1248,7 @@
 
 
 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RT>, r<RD>, <SHIFT>"
+"dsra32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
 *mipsV:
@@ -1270,7 +1270,7 @@
 }
 
 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
-"dsrav r<RT>, r<RD>, r<RS>"
+"dsrav r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
 *mipsV:
@@ -1824,7 +1824,7 @@
 }
 
 
-100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
+100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
 "lwu r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
-- 
2.30.2