From bb24369e5eff04024d60ce6e22abf52912808e4a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 4 Jun 2023 12:42:11 +0100
Subject: [PATCH]

---
 openpower/sv/ls010/trial_addi.mdwn | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/ls010/trial_addi.mdwn b/openpower/sv/ls010/trial_addi.mdwn
index 2429f5828..e5a19d870 100644
--- a/openpower/sv/ls010/trial_addi.mdwn
+++ b/openpower/sv/ls010/trial_addi.mdwn
@@ -9,11 +9,15 @@ Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
 * addi RT,RA,SI
 
 ```
-    DWI:
+    Defined Word-instruction:
         |    14 |   RT            |    RA       |     SI       |
         | 0     | 6               | 11          | 16        31 |
 ```
 
+* Operand RTL.RA <- `D-Form.RA`
+* Operand RTL.RT <- `D-Form.RT`
+* Operand RTL.SI <- `D-Form.SI`
+
 **Prefixed Add Immediate** MLS:D-form
 
 * paddi RT,RA,SI,R
@@ -28,19 +32,27 @@ Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
         | 0     | 6               | 11          | 16        31 |
 ```
 
+* Operand RTL.RA <- `D-Form.RA`
+* Operand RTL.RT <- `D-Form.RT`
+* Operand RTL.SI <- `MLS.si0 || MLS.si1`
+
 **Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
 
 * sv.addi RT,RA,SI 
 
 ```
-    Prefix: :
+    Prefix:
         |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
         | 0     | 6      | 8         | 17    26 | 27        31 |
-    Suffix:
+    Defined Word-instruction:
         |    14 |   RT            |    RA       |     SI       |
         | 0     | 6               | 11          | 16        31 |
 ```
 
+* Operand RTL.RA <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[0:2])`
+* Operand RTL.RT <- `SVP64_EXTRA3_DECODE(D-Form.RA, SVP64.RM.EXTRA[3:5])`
+* Operand RTL.SI <- `D-Form.SI`
+
 Pseudo-code:
 
 ```
-- 
2.30.2