From bb319eda3270ce3e61fb155495c463594fdb24a3 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Tue, 16 Mar 2021 07:55:48 -0300 Subject: [PATCH] Use symbolic values for subfields and bits --- src/soc/decoder/power_svp64_rm.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/decoder/power_svp64_rm.py b/src/soc/decoder/power_svp64_rm.py index ed1ed301..93d9be57 100644 --- a/src/soc/decoder/power_svp64_rm.py +++ b/src/soc/decoder/power_svp64_rm.py @@ -19,7 +19,7 @@ https://libre-soc.org/openpower/sv/svp64/ from nmigen import Elaboratable, Module, Signal from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype, SVP64PredMode, SVP64sat) -from soc.consts import EXTRA3 +from soc.consts import EXTRA3, SVP64MODE from soc.sv.svp64 import SVP64Rec from nmutil.util import sel @@ -85,14 +85,13 @@ class SVP64RMModeDecode(Elaboratable): # decode pieces of mode is_ldst = Signal() - mode2 = Signal(2) comb += is_ldst.eq(self.fn_in == Function.LDST) - comb += mode2.eq(mode[0:2]) + mode2 = sel(m, mode, SVP64MODE.MOD2) with m.Switch(mode2): with m.Case(0): # needs further decoding (LDST no mapreduce) with m.If(is_ldst): comb += self.mode.eq(SVP64RMMode.NORMAL) - with m.Elif(mode[3] == 1): + with m.Elif(mode[SVP64MODE.REDUCE]): comb += self.mode.eq(SVP64RMMode.MAPREDUCE) with m.Else(): comb += self.mode.eq(SVP64RMMode.NORMAL) -- 2.30.2