From bb33a88e3d4746470d3f969c6d764d20d726f9f1 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 10 Sep 2019 09:56:43 +0200 Subject: [PATCH] [ARM/FDPIC v6 12/24] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We call __aeabi_read_tp() to get the thread pointer. Since this is a function call, we have to restore the FDPIC register afterwards. 2019-09-10 Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. * config/arm/arm.md (FDPIC_REGNUM): New constant. (load_tp_soft_fdpic): New pattern. (load_tp_soft): Disable in FDPIC mode. Co-Authored-By: Mickaël Guêné From-SVN: r275574 --- gcc/ChangeLog | 10 ++++++++-- gcc/config/arm/arm.c | 13 ++++++++++++- gcc/config/arm/arm.md | 16 +++++++++++++++- 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eff014123ba..afe73b59f5d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,7 +1,14 @@ 2019-09-10 Christophe Lyon Mickaël Guêné - gcc/ + * config/arm/arm.c (arm_load_tp): Add FDPIC support. + * config/arm/arm.md (FDPIC_REGNUM): New constant. + (load_tp_soft_fdpic): New pattern. + (load_tp_soft): Disable in FDPIC mode. + +2019-09-10 Christophe Lyon + Mickaël Guêné + * config/arm/arm.c (tls_reloc): Add TLS_GD32_FDPIC, TLS_LDM32_FDPIC and TLS_IE32_FDPIC. (arm_call_tls_get_addr): Add FDPIC support. @@ -11,7 +18,6 @@ 2019-09-10 Christophe Lyon Mickaël Guêné - gcc/ * config/arm/arm.c (arm_asm_trampoline_template): Add FDPIC support. (arm_trampoline_init): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5f1d2d41795..c452771f473 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8685,7 +8685,18 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + emit_insn (gen_restore_pic_register_after_call(fdpic_reg, initial_fdpic_reg)); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 027febbaebb..918271d7ad5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -31,6 +31,7 @@ [(R0_REGNUM 0) ; First CORE register (R1_REGNUM 1) ; Second CORE register (R4_REGNUM 4) ; Fifth CORE register + (FDPIC_REGNUM 9) ; FDPIC register (IP_REGNUM 12) ; Scratch register (SP_REGNUM 13) ; Stack pointer (LR_REGNUM 14) ; Return address register @@ -11164,13 +11165,26 @@ (set_attr "type" "mrs")] ) +;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI FDPIC_REGNUM)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + ;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")] -- 2.30.2