From bb3509c4827c765b7bbe82936d97bc49ed99112a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Jan 2020 10:58:51 +0000 Subject: [PATCH] --- 3d_gpu/architecture.mdwn | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 3d_gpu/architecture.mdwn diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn new file mode 100644 index 000000000..4c7e1e4c8 --- /dev/null +++ b/3d_gpu/architecture.mdwn @@ -0,0 +1,9 @@ +# Top Level page for core architecture + +The primary design is based around the CDC 6600, specifically its Dependency Matrices which provide superscalar out-of-order execution and full register renaming with very little in the way of gates or power consumption. Modifying the 6600 concept to be multi-issue, thanks to help from Mitch Alsup, is near-trivial and an O(N) linear complexity. + +The basic principle: the front-end ISA is variable-length Vectorised, with a hardware-level for-loop in front of a predicated SIMD backend suite of ALUs. Instructions issued at the front-end are first SIMD-grouped, then the remaining "elements" (or groups of SIMD'd elements) are thrown at the multi-issue OoO execution engine and the augmented-6600 Matrices left to their own devices. + +Predication, branch speculation, register file bypass and exceptions all use the same mechanism: shadowing (thanks to Mitch for explaining how this is done). Shadowing holds a latch that prevents and prohibits the *write* commit phase of the OoO Matrices but not the *execution* phase, simply by hooking into GOWRITE. Once the result is definitely known to be able to proceed the shadow latch is dropped. + + -- 2.30.2