From bb48d3d500c065060b42d7c65e9cb646efafa7f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jul 2019 14:02:17 +0100 Subject: [PATCH] add comment --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 5f4eefc3..c17a2be6 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -360,6 +360,7 @@ class DivPipeCoreCalculateStage(Elaboratable): next_flag = pass_flags[i + 1] if i + 1 < radix else 0 flag = Signal(reset_less=True) test = Signal(reset_less=True) + # XXX TODO: check the width on this m.d.comb += test.eq((pass_flags[i] & ~next_flag)) m.d.comb += flag.eq(Mux(test, trial_compare_rhs_values[i], -- 2.30.2