From bb524860e21bbd216bc93a6545b73db47f5603c9 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Wed, 14 Apr 1999 01:43:07 +0200 Subject: [PATCH] i386.md (xorsi3): Do not output NOT instrctions on Pentium. * i386.md (xorsi3): Do not output NOT instrctions on Pentium. (xorqi3): Likewise. (xorhi3): Likewise. (notsi2): Likewise. (notqi2): Likewise. (nothi2): Likewise; do not output prefixed opcodes when possible. From-SVN: r26434 --- gcc/ChangeLog | 7 ++++ gcc/config/i386/i386.md | 89 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1d0c6e7bbba..4897998955c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ Wed Apr 14 00:18:22 1999 Jan Hubicka + * i386.md (xorsi3): Do not output NOT instrctions on Pentium. + (xorqi3): Likewise. + (xorhi3): Likewise. + (notsi2): Likewise. + (notqi2): Likewise. + (nothi2): Likewise; do not output prefixed opcodes when possible. + * i386.md (neghi2): Do not output prefixed opcode when possible. (ashlhi3): Likewise. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 270172424b0..5ad2c175b7b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4525,7 +4525,10 @@ byte_or_operation: byte_xor_operation: CC_STATUS_INIT; - if (intval == 0xff) + if (intval == 0xff + && (!TARGET_PENTIUM || optimize_size + || (GET_CODE (operands[0]) == MEM + && memory_address_length (XEXP (operands[0], 0)) != 0))) return AS1 (not%B0,%b0); if (intval != INTVAL (operands[2])) @@ -4541,7 +4544,10 @@ byte_xor_operation: if (REG_P (operands[0])) { CC_STATUS_INIT; - if (intval == 0xff) + if (intval == 0xff + && (!TARGET_PENTIUM || optimize_size + || (GET_CODE (operands[0]) == MEM + && memory_address_length (XEXP (operands[0], 0)) != 0))) return AS1 (not%B0,%h0); operands[2] = GEN_INT (intval); @@ -4598,7 +4604,10 @@ byte_xor_operation: if (INTVAL (operands[2]) & 0xffff0000) operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); - if (INTVAL (operands[2]) == 0xff) + if (INTVAL (operands[2]) == 0xff + && (!TARGET_PENTIUM || optimize_size + || (GET_CODE (operands[0]) == MEM + && memory_address_length (XEXP (operands[0], 0)) != 0))) return AS1 (not%B0,%b0); return AS2 (xor%B0,%2,%b0); @@ -4612,7 +4621,10 @@ byte_xor_operation: CC_STATUS_INIT; operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); - if (INTVAL (operands[2]) == 0xff) + if (INTVAL (operands[2]) == 0xff + && (!TARGET_PENTIUM || optimize_size + || (GET_CODE (operands[0]) == MEM + && memory_address_length (XEXP (operands[0], 0)) != 0))) return AS1 (not%B0,%h0); return AS2 (xor%B0,%2,%h0); @@ -4899,19 +4911,82 @@ byte_xor_operation: [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))] "" - "not%L0 %0") + "* +/* A Pentium NOT is not pariable. Output it only in case of complex + memory address, because XOR will be inpariable anyway because + of immediate/displacement rule. */ + +if (TARGET_PENTIUM && !optimize_size + && (GET_CODE (operands[0]) != MEM + || memory_address_length (XEXP (operands[0], 0)) == 0)) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xffffffff); + output_asm_insn (AS2 (xor%L0,%1,%0), xops); + RET; + } +else + return AS1 (not%L0,%0);") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))] "" - "not%W0 %0") + "* +/* A Pentium NOT is not pariable. Output it only in case of complex + memory address, because XOR will be inpariable anyway because + of immediate/displacement rule. */ + +if (TARGET_PENTIUM && !optimize_size + && (GET_CODE (operands[0]) != MEM + || memory_address_length (XEXP (operands[0], 0)) == 0)) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xffff); + if (REG_P (operands[0]) + && i386_cc_probably_useless_p (insn)) + { + CC_STATUS_INIT; + output_asm_insn (AS2 (xor%L0,%1,%k0), xops); + } + else + output_asm_insn (AS2 (xor%W0,%1,%0), xops); + RET; + } +else + { + if (REG_P (operands[0]) + && i386_cc_probably_useless_p (insn)) + { + CC_STATUS_INIT; + return AS1 (not%L0,%k0); + } + return AS1 (not%W0,%0); + }") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))] "" - "not%B0 %0") + "* +/* A Pentium NOT is not pariable. Output it only in case of complex + memory address, because XOR will be inpariable anyway because + of immediate/displacement rule. */ + +if (TARGET_PENTIUM && !optimize_size + && (GET_CODE (operands[0]) != MEM + || memory_address_length (XEXP (operands[0], 0)) == 0)) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (xor%B0,%1,%0), xops); + RET; + } +else + return AS1 (not%B0,%0);") ;;- arithmetic shift instructions -- 2.30.2