From bb52de845d213ea21f50467eebd24a6aec901254 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Feb 2021 12:37:45 +0000 Subject: [PATCH] add SVSTATE to CoreState --- src/soc/config/state.py | 2 ++ src/soc/sv/svstate.py | 22 +++++++++++----------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/soc/config/state.py b/src/soc/config/state.py index 3fc91967..ebc5bb86 100644 --- a/src/soc/config/state.py +++ b/src/soc/config/state.py @@ -1,5 +1,6 @@ from nmutil.iocontrol import RecordObject from nmigen import Signal +from soc.sv.svstate import SVSTATERec class CoreState(RecordObject): @@ -9,3 +10,4 @@ class CoreState(RecordObject): self.msr = Signal(64) # Machine Status Register (MSR) self.eint = Signal() # External Interrupt self.dec = Signal(64) # DEC SPR (again, for interrupt generation) + self.svstate = SVSTATERec(name) # Simple-V SVSTATE diff --git a/src/soc/sv/svstate.py b/src/soc/sv/svstate.py index 7bca63e3..c97efa48 100644 --- a/src/soc/sv/svstate.py +++ b/src/soc/sv/svstate.py @@ -15,17 +15,17 @@ https://libre-soc.org/openpower/sv/sprs/ | 30:31 | svstep | for svstep = 0..SUBVL-1 | """ -from nmigen import Record +from nmutil.iocontrol import RecordObject +from nmigen import Signal -class SVSTATERec(Record): + +class SVSTATERec(RecordObject): def __init__(self, name=None): - Record.__init__(self, layout=[("maxvl" : 7), - ("vl" : 7), - ("srcstep" : 7), - ("dststep" : 7), - ("subvl" : 2), - ("svstep" : 2)], name=name) - def ports(self): - return [self.maxvl, self.vl, self.srcstep, self.dststep, self.subvl, - self.svstep] + super().__init__(name=name) + self.maxvl = Signal(7) + self.vl = Signal(7) + self.srcstep = Signal(7) + self.dststep = Signal(7) + self.subvl = Signal(2) + self.svstep = Signal(2) -- 2.30.2