From bb70a2325a778220f110d4287d4f96b11c7d0acb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 May 2020 08:15:17 +0200 Subject: [PATCH] cpu/software: move CPU specific software from the BIOS to the CPU directories. This simplifies the integration of the CPUs' software, avoid complex switches in the code, and is a first step to make CPUs fully pluggable. The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o becomes crt0-ctr.o) so users building firmwares externally will have to update their Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o. --- .../cpu/blackparrot/boot-helper.S} | 0 .../cpu/blackparrot/crt0.S} | 0 litex/soc/cores/cpu/blackparrot/csr-defs.h | 8 + litex/soc/cores/cpu/blackparrot/irq.h | 51 +++++ .../base => cores/cpu/blackparrot}/system.h | 20 +- .../cpu/lm32/boot-helper.S} | 0 .../crt0-lm32.S => cores/cpu/lm32/crt0.S} | 0 litex/soc/cores/cpu/lm32/irq.h | 47 +++++ litex/soc/cores/cpu/lm32/system.h | 18 ++ .../cpu/microwatt/boot-helper.S} | 0 .../cpu/microwatt/crt0.S} | 0 litex/soc/cores/cpu/microwatt/irq.h | 4 + litex/soc/cores/cpu/microwatt/system.h | 18 ++ .../cpu/minerva/boot-helper.S} | 0 .../cpu/minerva/crt0.S} | 0 .../base => cores/cpu/minerva}/csr-defs.h | 7 - litex/soc/cores/cpu/minerva/irq.h | 45 ++++ litex/soc/cores/cpu/minerva/system.h | 42 ++++ .../cpu/mor1kx/boot-helper.S} | 0 .../crt0-mor1kx.S => cores/cpu/mor1kx/crt0.S} | 0 litex/soc/cores/cpu/mor1kx/irq.h | 44 ++++ litex/soc/cores/cpu/mor1kx/system.h | 33 +++ .../cpu/picorv32/boot-helper.S} | 0 .../cpu/picorv32/crt0.S} | 2 +- .../cpu/picorv32/extraops.S} | 0 litex/soc/cores/cpu/picorv32/irq.h | 67 ++++++ litex/soc/cores/cpu/picorv32/system.h | 18 ++ .../cpu/rocket/boot-helper.S} | 0 .../crt0-rocket.S => cores/cpu/rocket/crt0.S} | 0 litex/soc/cores/cpu/rocket/csr-defs.h | 8 + litex/soc/cores/cpu/rocket/irq.h | 50 +++++ litex/soc/cores/cpu/rocket/system.h | 42 ++++ .../cpu/serv/boot-helper.S} | 0 .../crt0-serv.S => cores/cpu/serv/crt0.S} | 0 litex/soc/cores/cpu/serv/irq.h | 4 + litex/soc/cores/cpu/serv/system.h | 18 ++ .../cpu/vexriscv/boot-helper.S} | 0 .../cpu/vexriscv/crt0.S} | 0 litex/soc/cores/cpu/vexriscv/csr-defs.h | 11 + litex/soc/cores/cpu/vexriscv/irq.h | 45 ++++ litex/soc/cores/cpu/vexriscv/system.h | 42 ++++ litex/soc/integration/export.py | 4 +- litex/soc/software/bios/Makefile | 14 +- litex/soc/software/bios/sdram.c | 1 + litex/soc/software/common.mak | 2 +- litex/soc/software/include/base/irq.h | 196 ------------------ litex/soc/software/libbase/Makefile | 8 +- 47 files changed, 636 insertions(+), 233 deletions(-) rename litex/soc/{software/bios/boot-helper-blackparrot.S => cores/cpu/blackparrot/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-blackparrot.S => cores/cpu/blackparrot/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/blackparrot/csr-defs.h create mode 100644 litex/soc/cores/cpu/blackparrot/irq.h rename litex/soc/{software/include/base => cores/cpu/blackparrot}/system.h (69%) rename litex/soc/{software/bios/boot-helper-lm32.S => cores/cpu/lm32/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-lm32.S => cores/cpu/lm32/crt0.S} (100%) mode change 100755 => 100644 create mode 100644 litex/soc/cores/cpu/lm32/irq.h create mode 100644 litex/soc/cores/cpu/lm32/system.h rename litex/soc/{software/bios/boot-helper-microwatt.S => cores/cpu/microwatt/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-microwatt.S => cores/cpu/microwatt/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/microwatt/irq.h create mode 100644 litex/soc/cores/cpu/microwatt/system.h rename litex/soc/{software/bios/boot-helper-minerva.S => cores/cpu/minerva/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-minerva.S => cores/cpu/minerva/crt0.S} (100%) rename litex/soc/{software/include/base => cores/cpu/minerva}/csr-defs.h (59%) create mode 100644 litex/soc/cores/cpu/minerva/irq.h create mode 100644 litex/soc/cores/cpu/minerva/system.h rename litex/soc/{software/bios/boot-helper-mor1kx.S => cores/cpu/mor1kx/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-mor1kx.S => cores/cpu/mor1kx/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/mor1kx/irq.h create mode 100644 litex/soc/cores/cpu/mor1kx/system.h rename litex/soc/{software/bios/boot-helper-picorv32.S => cores/cpu/picorv32/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-picorv32.S => cores/cpu/picorv32/crt0.S} (99%) rename litex/soc/{software/include/base/picorv32-extraops.S => cores/cpu/picorv32/extraops.S} (100%) create mode 100644 litex/soc/cores/cpu/picorv32/irq.h create mode 100644 litex/soc/cores/cpu/picorv32/system.h rename litex/soc/{software/bios/boot-helper-rocket.S => cores/cpu/rocket/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-rocket.S => cores/cpu/rocket/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/rocket/csr-defs.h create mode 100644 litex/soc/cores/cpu/rocket/irq.h create mode 100644 litex/soc/cores/cpu/rocket/system.h rename litex/soc/{software/bios/boot-helper-serv.S => cores/cpu/serv/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-serv.S => cores/cpu/serv/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/serv/irq.h create mode 100644 litex/soc/cores/cpu/serv/system.h rename litex/soc/{software/bios/boot-helper-vexriscv.S => cores/cpu/vexriscv/boot-helper.S} (100%) rename litex/soc/{software/libbase/crt0-vexriscv.S => cores/cpu/vexriscv/crt0.S} (100%) create mode 100644 litex/soc/cores/cpu/vexriscv/csr-defs.h create mode 100644 litex/soc/cores/cpu/vexriscv/irq.h create mode 100644 litex/soc/cores/cpu/vexriscv/system.h delete mode 100644 litex/soc/software/include/base/irq.h diff --git a/litex/soc/software/bios/boot-helper-blackparrot.S b/litex/soc/cores/cpu/blackparrot/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-blackparrot.S rename to litex/soc/cores/cpu/blackparrot/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-blackparrot.S b/litex/soc/cores/cpu/blackparrot/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-blackparrot.S rename to litex/soc/cores/cpu/blackparrot/crt0.S diff --git a/litex/soc/cores/cpu/blackparrot/csr-defs.h b/litex/soc/cores/cpu/blackparrot/csr-defs.h new file mode 100644 index 00000000..170bd454 --- /dev/null +++ b/litex/soc/cores/cpu/blackparrot/csr-defs.h @@ -0,0 +1,8 @@ +#ifndef CSR_DEFS__H +#define CSR_DEFS__H + +#define CSR_MSTATUS_MIE 0x8 + +#define CSR_DCACHE_INFO 0xCC0 + +#endif /* CSR_DEFS__H */ diff --git a/litex/soc/cores/cpu/blackparrot/irq.h b/litex/soc/cores/cpu/blackparrot/irq.h new file mode 100644 index 00000000..af5b7991 --- /dev/null +++ b/litex/soc/cores/cpu/blackparrot/irq.h @@ -0,0 +1,51 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which +// is programmed and queried via a set of MMIO registers. +// TODO: How about Blackparrot? Should be probably included in linux version + +#define PLIC_BASE 0x0c000000L // Base address and per-pin priority array +#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins +#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask +#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger +#define PLIC_CLAIM 0x0c200004L // Claim & completion register address + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */ +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */ +} + +static inline unsigned int irq_getmask(void) +{ + return 0; /* FIXME */ +} + +static inline void irq_setmask(unsigned int mask) +{ + /* FIXME */ +} + +static inline unsigned int irq_pending(void) +{ + return csr_readl(PLIC_PENDING) >> 1; /* FIXME */ +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/software/include/base/system.h b/litex/soc/cores/cpu/blackparrot/system.h similarity index 69% rename from litex/soc/software/include/base/system.h rename to litex/soc/cores/cpu/blackparrot/system.h index ef3bf45b..cccdb54d 100644 --- a/litex/soc/software/include/base/system.h +++ b/litex/soc/cores/cpu/blackparrot/system.h @@ -11,25 +11,8 @@ void flush_l2_cache(void); void busy_wait(unsigned int ms); -#ifdef __or1k__ -#include -static inline unsigned long mfspr(unsigned long add) -{ - unsigned long ret; - - __asm__ __volatile__ ("l.mfspr %0,%1,0" : "=r" (ret) : "r" (add)); - - return ret; -} - -static inline void mtspr(unsigned long add, unsigned long val) -{ - __asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val)); -} -#endif - -#if defined(__vexriscv__) || defined(__minerva__) || defined(__rocket__) || defined(__blackparrot__) #include + #define csrr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) @@ -51,7 +34,6 @@ static inline void mtspr(unsigned long add, unsigned long val) asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ else \ asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) -#endif #ifdef __cplusplus } diff --git a/litex/soc/software/bios/boot-helper-lm32.S b/litex/soc/cores/cpu/lm32/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-lm32.S rename to litex/soc/cores/cpu/lm32/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-lm32.S b/litex/soc/cores/cpu/lm32/crt0.S old mode 100755 new mode 100644 similarity index 100% rename from litex/soc/software/libbase/crt0-lm32.S rename to litex/soc/cores/cpu/lm32/crt0.S diff --git a/litex/soc/cores/cpu/lm32/irq.h b/litex/soc/cores/cpu/lm32/irq.h new file mode 100644 index 00000000..dd9477fa --- /dev/null +++ b/litex/soc/cores/cpu/lm32/irq.h @@ -0,0 +1,47 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +static inline unsigned int irq_getie(void) +{ + unsigned int ie; + __asm__ __volatile__("rcsr %0, IE" : "=r" (ie)); + return ie; +} + +static inline void irq_setie(unsigned int ie) +{ + __asm__ __volatile__("wcsr IE, %0" : : "r" (ie)); +} + +static inline unsigned int irq_getmask(void) +{ + unsigned int mask; + __asm__ __volatile__("rcsr %0, IM" : "=r" (mask)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + __asm__ __volatile__("wcsr IM, %0" : : "r" (mask)); +} + +static inline unsigned int irq_pending(void) +{ + unsigned int pending; + __asm__ __volatile__("rcsr %0, IP" : "=r" (pending)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/lm32/system.h b/litex/soc/cores/cpu/lm32/system.h new file mode 100644 index 00000000..989c9c62 --- /dev/null +++ b/litex/soc/cores/cpu/lm32/system.h @@ -0,0 +1,18 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-microwatt.S b/litex/soc/cores/cpu/microwatt/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-microwatt.S rename to litex/soc/cores/cpu/microwatt/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-microwatt.S b/litex/soc/cores/cpu/microwatt/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-microwatt.S rename to litex/soc/cores/cpu/microwatt/crt0.S diff --git a/litex/soc/cores/cpu/microwatt/irq.h b/litex/soc/cores/cpu/microwatt/irq.h new file mode 100644 index 00000000..7374cf50 --- /dev/null +++ b/litex/soc/cores/cpu/microwatt/irq.h @@ -0,0 +1,4 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/microwatt/system.h b/litex/soc/cores/cpu/microwatt/system.h new file mode 100644 index 00000000..989c9c62 --- /dev/null +++ b/litex/soc/cores/cpu/microwatt/system.h @@ -0,0 +1,18 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-minerva.S b/litex/soc/cores/cpu/minerva/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-minerva.S rename to litex/soc/cores/cpu/minerva/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-minerva.S b/litex/soc/cores/cpu/minerva/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-minerva.S rename to litex/soc/cores/cpu/minerva/crt0.S diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/cores/cpu/minerva/csr-defs.h similarity index 59% rename from litex/soc/software/include/base/csr-defs.h rename to litex/soc/cores/cpu/minerva/csr-defs.h index 75c8e043..5f5ea847 100644 --- a/litex/soc/software/include/base/csr-defs.h +++ b/litex/soc/cores/cpu/minerva/csr-defs.h @@ -3,15 +3,8 @@ #define CSR_MSTATUS_MIE 0x8 -#if defined (__vexriscv__) -#define CSR_IRQ_MASK 0xBC0 -#define CSR_IRQ_PENDING 0xFC0 -#endif - -#if defined (__minerva__) #define CSR_IRQ_MASK 0x330 #define CSR_IRQ_PENDING 0x360 -#endif #define CSR_DCACHE_INFO 0xCC0 diff --git a/litex/soc/cores/cpu/minerva/irq.h b/litex/soc/cores/cpu/minerva/irq.h new file mode 100644 index 00000000..69bac122 --- /dev/null +++ b/litex/soc/cores/cpu/minerva/irq.h @@ -0,0 +1,45 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +static inline unsigned int irq_getmask(void) +{ + unsigned int mask; + asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); +} + +static inline unsigned int irq_pending(void) +{ + unsigned int pending; + asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/minerva/system.h b/litex/soc/cores/cpu/minerva/system.h new file mode 100644 index 00000000..cccdb54d --- /dev/null +++ b/litex/soc/cores/cpu/minerva/system.h @@ -0,0 +1,42 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#include + +#define csrr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define csrw(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define csrs(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + +#define csrc(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-mor1kx.S b/litex/soc/cores/cpu/mor1kx/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-mor1kx.S rename to litex/soc/cores/cpu/mor1kx/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-mor1kx.S b/litex/soc/cores/cpu/mor1kx/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-mor1kx.S rename to litex/soc/cores/cpu/mor1kx/crt0.S diff --git a/litex/soc/cores/cpu/mor1kx/irq.h b/litex/soc/cores/cpu/mor1kx/irq.h new file mode 100644 index 00000000..acc64c0a --- /dev/null +++ b/litex/soc/cores/cpu/mor1kx/irq.h @@ -0,0 +1,44 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +static inline unsigned int irq_getie(void) +{ + return !!(mfspr(SPR_SR) & SPR_SR_IEE); +} + +static inline void irq_setie(unsigned int ie) +{ + if (ie & 0x1) + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + else + mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE); +} + +static inline unsigned int irq_getmask(void) +{ + return mfspr(SPR_PICMR); +} + +static inline void irq_setmask(unsigned int mask) +{ + mtspr(SPR_PICMR, mask); +} + +static inline unsigned int irq_pending(void) +{ + return mfspr(SPR_PICSR); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/mor1kx/system.h b/litex/soc/cores/cpu/mor1kx/system.h new file mode 100644 index 00000000..004a00e3 --- /dev/null +++ b/litex/soc/cores/cpu/mor1kx/system.h @@ -0,0 +1,33 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#include +static inline unsigned long mfspr(unsigned long add) +{ + unsigned long ret; + + __asm__ __volatile__ ("l.mfspr %0,%1,0" : "=r" (ret) : "r" (add)); + + return ret; +} + +static inline void mtspr(unsigned long add, unsigned long val) +{ + __asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-picorv32.S b/litex/soc/cores/cpu/picorv32/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-picorv32.S rename to litex/soc/cores/cpu/picorv32/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-picorv32.S b/litex/soc/cores/cpu/picorv32/crt0.S similarity index 99% rename from litex/soc/software/libbase/crt0-picorv32.S rename to litex/soc/cores/cpu/picorv32/crt0.S index 3f7a4f5c..49883ed0 100644 --- a/litex/soc/software/libbase/crt0-picorv32.S +++ b/litex/soc/cores/cpu/picorv32/crt0.S @@ -5,7 +5,7 @@ * purpose with or without fee is hereby granted. */ -#include "picorv32-extraops.S" +#include "extraops.S" /* * Interrupt vector. diff --git a/litex/soc/software/include/base/picorv32-extraops.S b/litex/soc/cores/cpu/picorv32/extraops.S similarity index 100% rename from litex/soc/software/include/base/picorv32-extraops.S rename to litex/soc/cores/cpu/picorv32/extraops.S diff --git a/litex/soc/cores/cpu/picorv32/irq.h b/litex/soc/cores/cpu/picorv32/irq.h new file mode 100644 index 00000000..0badb132 --- /dev/null +++ b/litex/soc/cores/cpu/picorv32/irq.h @@ -0,0 +1,67 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +// PicoRV32 has a very limited interrupt support, implemented via custom +// instructions. It also doesn't have a global interrupt enable/disable, so +// we have to emulate it via saving and restoring a mask and using 0/~1 as a +// hardware mask. +// Due to all this somewhat low-level mess, all of the glue is implemented in +// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts +// managed by this layer, do not call interrupt instructions directly, as the +// state will go out of sync with the hardware. + +// Read only. +extern unsigned int _irq_pending; +// Read only. +extern unsigned int _irq_mask; +// Read only. +extern unsigned int _irq_enabled; +extern void _irq_enable(void); +extern void _irq_disable(void); +extern void _irq_setmask(unsigned int); + +static inline unsigned int irq_getie(void) +{ + return _irq_enabled != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if (ie & 0x1) + _irq_enable(); + else + _irq_disable(); +} + +static inline unsigned int irq_getmask(void) +{ + // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how + // LiteX sees things. + return ~_irq_mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how + // LiteX sees things. + _irq_setmask(~mask); +} + +static inline unsigned int irq_pending(void) +{ + return _irq_pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/picorv32/system.h b/litex/soc/cores/cpu/picorv32/system.h new file mode 100644 index 00000000..989c9c62 --- /dev/null +++ b/litex/soc/cores/cpu/picorv32/system.h @@ -0,0 +1,18 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-rocket.S b/litex/soc/cores/cpu/rocket/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-rocket.S rename to litex/soc/cores/cpu/rocket/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-rocket.S b/litex/soc/cores/cpu/rocket/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-rocket.S rename to litex/soc/cores/cpu/rocket/crt0.S diff --git a/litex/soc/cores/cpu/rocket/csr-defs.h b/litex/soc/cores/cpu/rocket/csr-defs.h new file mode 100644 index 00000000..170bd454 --- /dev/null +++ b/litex/soc/cores/cpu/rocket/csr-defs.h @@ -0,0 +1,8 @@ +#ifndef CSR_DEFS__H +#define CSR_DEFS__H + +#define CSR_MSTATUS_MIE 0x8 + +#define CSR_DCACHE_INFO 0xCC0 + +#endif /* CSR_DEFS__H */ diff --git a/litex/soc/cores/cpu/rocket/irq.h b/litex/soc/cores/cpu/rocket/irq.h new file mode 100644 index 00000000..9548b01f --- /dev/null +++ b/litex/soc/cores/cpu/rocket/irq.h @@ -0,0 +1,50 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which +// is programmed and queried via a set of MMIO registers. + +#define PLIC_BASE 0x0c000000L // Base address and per-pin priority array +#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins +#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask +#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger +#define PLIC_CLAIM 0x0c200004L // Claim & completion register address + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +static inline unsigned int irq_getmask(void) +{ + return *((unsigned int *)PLIC_ENABLED) >> 1; +} + +static inline void irq_setmask(unsigned int mask) +{ + *((unsigned int *)PLIC_ENABLED) = mask << 1; +} + +static inline unsigned int irq_pending(void) +{ + return *((unsigned int *)PLIC_PENDING) >> 1; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/rocket/system.h b/litex/soc/cores/cpu/rocket/system.h new file mode 100644 index 00000000..cccdb54d --- /dev/null +++ b/litex/soc/cores/cpu/rocket/system.h @@ -0,0 +1,42 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#include + +#define csrr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define csrw(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define csrs(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + +#define csrc(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-serv.S b/litex/soc/cores/cpu/serv/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-serv.S rename to litex/soc/cores/cpu/serv/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-serv.S b/litex/soc/cores/cpu/serv/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-serv.S rename to litex/soc/cores/cpu/serv/crt0.S diff --git a/litex/soc/cores/cpu/serv/irq.h b/litex/soc/cores/cpu/serv/irq.h new file mode 100644 index 00000000..7374cf50 --- /dev/null +++ b/litex/soc/cores/cpu/serv/irq.h @@ -0,0 +1,4 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/serv/system.h b/litex/soc/cores/cpu/serv/system.h new file mode 100644 index 00000000..989c9c62 --- /dev/null +++ b/litex/soc/cores/cpu/serv/system.h @@ -0,0 +1,18 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/software/bios/boot-helper-vexriscv.S b/litex/soc/cores/cpu/vexriscv/boot-helper.S similarity index 100% rename from litex/soc/software/bios/boot-helper-vexriscv.S rename to litex/soc/cores/cpu/vexriscv/boot-helper.S diff --git a/litex/soc/software/libbase/crt0-vexriscv.S b/litex/soc/cores/cpu/vexriscv/crt0.S similarity index 100% rename from litex/soc/software/libbase/crt0-vexriscv.S rename to litex/soc/cores/cpu/vexriscv/crt0.S diff --git a/litex/soc/cores/cpu/vexriscv/csr-defs.h b/litex/soc/cores/cpu/vexriscv/csr-defs.h new file mode 100644 index 00000000..d98e8dfb --- /dev/null +++ b/litex/soc/cores/cpu/vexriscv/csr-defs.h @@ -0,0 +1,11 @@ +#ifndef CSR_DEFS__H +#define CSR_DEFS__H + +#define CSR_MSTATUS_MIE 0x8 + +#define CSR_IRQ_MASK 0xBC0 +#define CSR_IRQ_PENDING 0xFC0 + +#define CSR_DCACHE_INFO 0xCC0 + +#endif /* CSR_DEFS__H */ diff --git a/litex/soc/cores/cpu/vexriscv/irq.h b/litex/soc/cores/cpu/vexriscv/irq.h new file mode 100644 index 00000000..69bac122 --- /dev/null +++ b/litex/soc/cores/cpu/vexriscv/irq.h @@ -0,0 +1,45 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +static inline unsigned int irq_getmask(void) +{ + unsigned int mask; + asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); +} + +static inline unsigned int irq_pending(void) +{ + unsigned int pending; + asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h new file mode 100644 index 00000000..cccdb54d --- /dev/null +++ b/litex/soc/cores/cpu/vexriscv/system.h @@ -0,0 +1,42 @@ +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +void flush_cpu_icache(void); +void flush_cpu_dcache(void); +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + +#include + +#define csrr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define csrw(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define csrs(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + +#define csrc(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_H */ diff --git a/litex/soc/integration/export.py b/litex/soc/integration/export.py index 2761443a..9117d82e 100644 --- a/litex/soc/integration/export.py +++ b/litex/soc/integration/export.py @@ -15,6 +15,7 @@ import os import json +import inspect from shutil import which from sysconfig import get_platform @@ -85,7 +86,8 @@ def get_cpu_mak(cpu, compile_software): ("CPU", cpu.name), ("CPUFLAGS", flags), ("CPUENDIANNESS", cpu.endianness), - ("CLANG", str(int(clang))) + ("CLANG", str(int(clang))), + ("CPU_DIRECTORY", os.path.dirname(inspect.getfile(cpu.__class__))), ] diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile index 12510a71..cc3b973a 100755 --- a/litex/soc/software/bios/Makefile +++ b/litex/soc/software/bios/Makefile @@ -2,7 +2,7 @@ include ../include/generated/variables.mak include $(SOC_DIRECTORY)/software/common.mak ifeq ($(CPU),blackparrot) -BP_LIBS = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0 +BP_LIBS = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0 BP_FLAGS = -lgcc endif # Permit TFTP_SERVER_PORT override from shell environment / command line @@ -10,7 +10,7 @@ ifdef TFTP_SERVER_PORT CFLAGS += -DTFTP_SERVER_PORT=$(TFTP_SERVER_PORT) endif -OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper-$(CPU).o boot.o +OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper.o boot.o all: bios.bin $(PYTHON) -m litex.soc.software.memusage bios.elf $(CURDIR)/../include/generated/regions.ld $(TRIPLE) @@ -29,9 +29,9 @@ endif bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS) -%.elf: ../libbase/crt0-$(CPU)-ctr.o ../libnet/libnet.a ../libbase/libbase-nofloat.a ../libcompiler_rt/libcompiler_rt.a +%.elf: ../libbase/crt0-ctr.o ../libnet/libnet.a ../libbase/libbase-nofloat.a ../libcompiler_rt/libcompiler_rt.a $(LD) $(LDFLAGS) -T $(BIOS_DIRECTORY)/linker.ld -N -o $@ \ - ../libbase/crt0-$(CPU)-ctr.o \ + ../libbase/crt0-ctr.o \ $(OBJECTS) \ -L../libnet \ -L../libbase \ @@ -39,7 +39,7 @@ bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS) $(BP_LIBS) \ -lnet -lbase-nofloat -lcompiler_rt \ $(BP_FLAGS) - + ifneq ($(OS),Windows_NT) chmod -x $@ endif @@ -53,6 +53,10 @@ endif %.o: $(BIOS_DIRECTORY)/%.S $(assemble) +boot-helper.o: $(CPU_DIRECTORY)/boot-helper.S + cp $(CPU_DIRECTORY)/boot-helper.S $(BIOS_DIRECTORY)/boot-helper.S + $(assemble) + clean: $(RM) $(OBJECTS) bios.elf bios.bin .*~ *~ diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c index 8d8ddfef..513a1266 100644 --- a/litex/soc/software/bios/sdram.c +++ b/litex/soc/software/bios/sdram.c @@ -29,6 +29,7 @@ __attribute__((unused)) static void cdelay(int i) { + /* FIXME: move nop definitions to CPUs */ while(i > 0) { #if defined (__lm32__) __asm__ volatile("nop"); diff --git a/litex/soc/software/common.mak b/litex/soc/software/common.mak index 18fc50c3..83f1aba4 100644 --- a/litex/soc/software/common.mak +++ b/litex/soc/software/common.mak @@ -45,7 +45,7 @@ DEPFLAGS += -MD -MP # Toolchain options # -INCLUDES = -I$(SOC_DIRECTORY)/software/include/base -I$(SOC_DIRECTORY)/software/include -I$(SOC_DIRECTORY)/common -I$(BUILDINC_DIRECTORY) +INCLUDES = -I$(SOC_DIRECTORY)/software/include/base -I$(SOC_DIRECTORY)/software/include -I$(SOC_DIRECTORY)/common -I$(BUILDINC_DIRECTORY) -I$(CPU_DIRECTORY) COMMONFLAGS = $(DEPFLAGS) -Os $(CPUFLAGS) -g3 -fomit-frame-pointer -Wall -fno-builtin -nostdinc $(INCLUDES) CFLAGS = $(COMMONFLAGS) -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes CXXFLAGS = $(COMMONFLAGS) -std=c++11 -I$(SOC_DIRECTORY)/software/include/basec++ -fexceptions -fno-rtti -ffreestanding diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h deleted file mode 100644 index 9fd8e180..00000000 --- a/litex/soc/software/include/base/irq.h +++ /dev/null @@ -1,196 +0,0 @@ -#ifndef __IRQ_H -#define __IRQ_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifdef CONFIG_CPU_HAS_INTERRUPT - -#ifdef __picorv32__ -// PicoRV32 has a very limited interrupt support, implemented via custom -// instructions. It also doesn't have a global interrupt enable/disable, so -// we have to emulate it via saving and restoring a mask and using 0/~1 as a -// hardware mask. -// Due to all this somewhat low-level mess, all of the glue is implemented in -// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts -// managed by this layer, do not call interrupt instructions directly, as the -// state will go out of sync with the hardware. - -// Read only. -extern unsigned int _irq_pending; -// Read only. -extern unsigned int _irq_mask; -// Read only. -extern unsigned int _irq_enabled; -extern void _irq_enable(void); -extern void _irq_disable(void); -extern void _irq_setmask(unsigned int); -#endif - -#ifdef __rocket__ -// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which -// is programmed and queried via a set of MMIO registers. - -#define PLIC_BASE 0x0c000000L // Base address and per-pin priority array -#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins -#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask -#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger -#define PLIC_CLAIM 0x0c200004L // Claim & completion register address -#endif /* __rocket__ */ - - -#ifdef __blackparrot__ -// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which -// is programmed and queried via a set of MMIO registers. -// TODO: How about Blackparrot? Should be probably included in linux version - -#define PLIC_BASE 0x0c000000L // Base address and per-pin priority array -#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins -#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask -#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger -#define PLIC_CLAIM 0x0c200004L // Claim & completion register address -#endif /* __blackparrot__ */ - - - -static inline unsigned int irq_getie(void) -{ -#if defined (__lm32__) - unsigned int ie; - __asm__ __volatile__("rcsr %0, IE" : "=r" (ie)); - return ie; -#elif defined (__or1k__) - return !!(mfspr(SPR_SR) & SPR_SR_IEE); -#elif defined (__picorv32__) - return _irq_enabled != 0; -#elif defined (__vexriscv__) - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; -#elif defined (__minerva__) - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; -#elif defined (__rocket__) - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; -#elif defined (__blackparrot__) - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */ -#else -#error Unsupported architecture -#endif -} - -static inline void irq_setie(unsigned int ie) -{ -#if defined (__lm32__) - __asm__ __volatile__("wcsr IE, %0" : : "r" (ie)); -#elif defined (__or1k__) - if (ie & 0x1) - mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); - else - mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE); -#elif defined (__picorv32__) - if (ie & 0x1) - _irq_enable(); - else - _irq_disable(); -#elif defined (__vexriscv__) - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); -#elif defined (__minerva__) - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); -#elif defined (__rocket__) - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); -#elif defined (__blackparrot__) - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */ -#else -#error Unsupported architecture -#endif -} - -static inline unsigned int irq_getmask(void) -{ -#if defined (__lm32__) - unsigned int mask; - __asm__ __volatile__("rcsr %0, IM" : "=r" (mask)); - return mask; -#elif defined (__or1k__) - return mfspr(SPR_PICMR); -#elif defined (__picorv32__) - // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how - // LiteX sees things. - return ~_irq_mask; -#elif defined (__vexriscv__) - unsigned int mask; - asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); - return mask; -#elif defined (__minerva__) - unsigned int mask; - asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); - return mask; -#elif defined (__rocket__) - return *((unsigned int *)PLIC_ENABLED) >> 1; -#elif defined (__blackparrot__) - return 0; /* FIXME */ -#else -#error Unsupported architecture -#endif -} - -static inline void irq_setmask(unsigned int mask) -{ -#if defined (__lm32__) - __asm__ __volatile__("wcsr IM, %0" : : "r" (mask)); -#elif defined (__or1k__) - mtspr(SPR_PICMR, mask); -#elif defined (__picorv32__) - // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how - // LiteX sees things. - _irq_setmask(~mask); -#elif defined (__vexriscv__) - asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); -#elif defined (__minerva__) - asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); -#elif defined (__rocket__) - *((unsigned int *)PLIC_ENABLED) = mask << 1; -#elif defined (__blackparrot__) - /* FIXME */ -#else -#error Unsupported architecture -#endif -} - -static inline unsigned int irq_pending(void) -{ -#if defined (__lm32__) - unsigned int pending; - __asm__ __volatile__("rcsr %0, IP" : "=r" (pending)); - return pending; -#elif defined (__or1k__) - return mfspr(SPR_PICSR); -#elif defined (__picorv32__) - return _irq_pending; -#elif defined (__vexriscv__) - unsigned int pending; - asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); - return pending; -#elif defined (__minerva__) - unsigned int pending; - asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); - return pending; -#elif defined (__rocket__) - return *((unsigned int *)PLIC_PENDING) >> 1; -#elif defined (__blackparrot__) - return csr_readl(PLIC_PENDING) >> 1; /* FIXME */ -#else -#error Unsupported architecture -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif - -#endif /* __IRQ_H */ diff --git a/litex/soc/software/libbase/Makefile b/litex/soc/software/libbase/Makefile index e3a80a03..e81a5316 100755 --- a/litex/soc/software/libbase/Makefile +++ b/litex/soc/software/libbase/Makefile @@ -4,7 +4,7 @@ include $(SOC_DIRECTORY)/software/common.mak OBJECTS=exception.o libc.o errno.o crc16.o crc32.o console.o \ system.o id.o uart.o time.o qsort.o strtod.o spiflash.o spisdcard.o strcasecmp.o mdio.o -all: crt0-$(CPU)-ctr.o crt0-$(CPU)-xip.o libbase.a libbase-nofloat.a +all: crt0-ctr.o crt0-xip.o libbase.a libbase-nofloat.a libbase.a: $(OBJECTS) vsnprintf.o $(AR) crs libbase.a $(OBJECTS) vsnprintf.o @@ -24,10 +24,12 @@ vsnprintf-nofloat.o: $(LIBBASE_DIRECTORY)/vsnprintf.c %.o: $(LIBBASE_DIRECTORY)/%.S $(assemble) -crt0-$(CPU)-ctr.o: $(LIBBASE_DIRECTORY)/crt0-$(CPU).S +crt0-ctr.o: $(CPU_DIRECTORY)/crt0.S + cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-crt.S $(assemble) -crt0-$(CPU)-xip.o: $(LIBBASE_DIRECTORY)/crt0-$(CPU).S +crt0-xip.o: $(CPU_DIRECTORY)/crt0.S + cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-xip.S $(CC) -c -DEXECUTE_IN_PLACE $(CFLAGS) -o $@ $< .PHONY: all clean -- 2.30.2