From bbf58cd6417d6c87ab7f6d660f57f37a0573e263 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 26 Jun 2020 15:36:41 -0400 Subject: [PATCH] Modify pi2ls so it passes the portinterface unit tests --- src/soc/experiment/pi2ls.py | 16 ++++++++++++++-- src/soc/experiment/test/test_pi2ls.py | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 3fe43b73..548ac5e5 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -51,6 +51,8 @@ class Pi2LSUI(Elaboratable): pi, lsui, addrbits = self.pi, self.lsui, self.addrbits m.submodules.lenexp = lenexp = LenExpand(self.addrbits, 8) + ld_in_progress = Signal(reset=0) + m.d.comb += lsui.x_ld_i.eq(pi.is_ld_i) m.d.comb += lsui.x_st_i.eq(pi.is_st_i) m.d.comb += pi.busy_o.eq(lsui.x_busy_o) @@ -68,10 +70,20 @@ class Pi2LSUI(Elaboratable): with m.If(pi.is_ld_i): m.d.comb += pi.ld.data.eq(lsui.m_ld_data_o) - m.d.comb += pi.ld.ok.eq(1) # TODO whether this should be one cycle + # remember we're in the process of loading + m.d.sync += ld_in_progress.eq(1) + + # If a load happened on the previous cycle and the memory is + # not busy, that means it returned the data from the load. In + # that case ld.ok should be set andwe can clear the + # ld_in_progress flag + with m.If(ld_in_progress & ~lsui.x_busy_o): + m.d.comb += pi.ld.ok.eq(1) + m.d.sync += ld_in_progress.eq(0) + with m.Else(): + m.d.comb += pi.ld.ok.eq(0) with m.If(pi.is_st_i & pi.st.ok): m.d.comb += lsui.x_st_data_i.eq(pi.st.data) return m - diff --git a/src/soc/experiment/test/test_pi2ls.py b/src/soc/experiment/test/test_pi2ls.py index eda2f515..a1ea7633 100644 --- a/src/soc/experiment/test/test_pi2ls.py +++ b/src/soc/experiment/test/test_pi2ls.py @@ -84,7 +84,7 @@ def l0_cache_ld(dut, addr, datalen, expected): yield port1.pi.addr.ok.eq(1) # set ok yield Settle() yield from wait_addr(port1) # wait until addr ok - + yield yield from wait_ldok(port1) # wait until ld ok data = yield port1.pi.ld.data -- 2.30.2