From bc00fd0179194c04d95b43365cc4adb54d9fb511 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 19 Jun 2022 14:55:20 +0100 Subject: [PATCH] spelling --- openpower/sv.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index 35d1502cc..02f78aecb 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -19,7 +19,7 @@ and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual explicit Vector opcode exists in SV, at all**. It is suitable for low-power Embedded and DSP Workloads as much as it is for power-efficient -Suoercomputing. +Supercomputing. Fundamental design principles: -- 2.30.2