From bc23060fe364326aa7560689409e2911324e9241 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Thu, 7 Jun 2018 15:00:27 +0530 Subject: [PATCH] arch-power: Add fixed-point logical extend sign instructions This adds the following logical instructions: * Extend Sign Word (extsw[.]) Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b Signed-off-by: Sandipan Das --- src/arch/power/insts/integer.cc | 1 + src/arch/power/isa/decoder.isa | 1 + 2 files changed, 2 insertions(+) diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index d3672472c..f87afa282 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -292,6 +292,7 @@ IntLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printSecondSrc = false; } else if (!myMnemonic.compare("extsb") || !myMnemonic.compare("extsh") || + !myMnemonic.compare("extsw") || !myMnemonic.compare("cntlzw")) { printSecondSrc = false; } diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index d80846f99..6390017af 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -513,6 +513,7 @@ decode PO default Unknown::unknown() { 412: orc({{ Ra = Rs | ~Rb; }}, true); 954: extsb({{ Ra = Rs_sb; }}, true); 922: extsh({{ Ra = Rs_sh; }}, true); + 986: extsw({{ Ra = Rs_sw; }}, true); 26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true); 508: cmpb({{ -- 2.30.2