From bc51f15b320235c06bf666cf870e9995d6cecc6b Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 28 Jun 2013 14:50:30 -0700 Subject: [PATCH] i965: Pull 3D texture layout code out into a helper function. A bit cleaner than having it in one giant function. Signed-off-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 159 +++++++++++---------- 1 file changed, 82 insertions(+), 77 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index f0736fa976f..fc929f855a5 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -66,6 +66,86 @@ brw_miptree_layout_texture_array(struct intel_context *intel, mt->total_height = qpitch * mt->physical_depth0; } +static void +brw_miptree_layout_texture_3d(struct intel_context *intel, + struct intel_mipmap_tree *mt) +{ + GLuint width = mt->physical_width0; + GLuint height = mt->physical_height0; + GLuint depth = mt->physical_depth0; + GLuint pack_x_pitch, pack_x_nr; + GLuint pack_y_pitch; + GLuint level; + + mt->total_height = 0; + + if (mt->compressed) { + mt->total_width = ALIGN(width, mt->align_w); + pack_y_pitch = (height + 3) / 4; + } else { + mt->total_width = mt->physical_width0; + pack_y_pitch = ALIGN(mt->physical_height0, mt->align_h); + } + + pack_x_pitch = width; + pack_x_nr = 1; + + for (level = mt->first_level ; level <= mt->last_level ; level++) { + GLint x = 0; + GLint y = 0; + GLint q, j; + + intel_miptree_set_level_info(mt, level, + 0, mt->total_height, + width, height, depth); + + for (q = 0; q < depth; /* empty */) { + for (j = 0; j < pack_x_nr && q < depth; j++, q++) { + intel_miptree_set_image_offset(mt, level, q, x, y); + x += pack_x_pitch; + } + if (x > mt->total_width) + mt->total_width = x; + + x = 0; + y += pack_y_pitch; + } + + mt->total_height += y; + width = minify(width, 1); + height = minify(height, 1); + if (mt->target == GL_TEXTURE_3D) + depth = minify(depth, 1); + + if (mt->compressed) { + pack_y_pitch = (height + 3) / 4; + + if (pack_x_pitch > ALIGN(width, mt->align_w)) { + pack_x_pitch = ALIGN(width, mt->align_w); + pack_x_nr <<= 1; + } + } else { + pack_x_nr <<= 1; + if (pack_x_pitch > 4) { + pack_x_pitch >>= 1; + } + + if (pack_y_pitch > 2) { + pack_y_pitch >>= 1; + pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h); + } + } + } + + /* The 965's sampler lays cachelines out according to how accesses + * in the texture surfaces run, so they may be "vertical" through + * memory. As a result, the docs say in Surface Padding Requirements: + * Sampling Engine Surfaces that two extra rows of padding are required. + */ + if (mt->target == GL_TEXTURE_CUBE_MAP) + mt->total_height += 2; +} + void brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt) { @@ -87,84 +167,9 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt) assert(mt->physical_depth0 == 6); /* FALLTHROUGH */ - case GL_TEXTURE_3D: { - GLuint width = mt->physical_width0; - GLuint height = mt->physical_height0; - GLuint depth = mt->physical_depth0; - GLuint pack_x_pitch, pack_x_nr; - GLuint pack_y_pitch; - GLuint level; - - mt->total_height = 0; - - if (mt->compressed) { - mt->total_width = ALIGN(width, mt->align_w); - pack_y_pitch = (height + 3) / 4; - } else { - mt->total_width = mt->physical_width0; - pack_y_pitch = ALIGN(mt->physical_height0, mt->align_h); - } - - pack_x_pitch = width; - pack_x_nr = 1; - - for (level = mt->first_level ; level <= mt->last_level ; level++) { - GLint x = 0; - GLint y = 0; - GLint q, j; - - intel_miptree_set_level_info(mt, level, - 0, mt->total_height, - width, height, depth); - - for (q = 0; q < depth; /* empty */) { - for (j = 0; j < pack_x_nr && q < depth; j++, q++) { - intel_miptree_set_image_offset(mt, level, q, x, y); - x += pack_x_pitch; - } - if (x > mt->total_width) - mt->total_width = x; - - x = 0; - y += pack_y_pitch; - } - - - mt->total_height += y; - width = minify(width, 1); - height = minify(height, 1); - if (mt->target == GL_TEXTURE_3D) - depth = minify(depth, 1); - - if (mt->compressed) { - pack_y_pitch = (height + 3) / 4; - - if (pack_x_pitch > ALIGN(width, mt->align_w)) { - pack_x_pitch = ALIGN(width, mt->align_w); - pack_x_nr <<= 1; - } - } else { - pack_x_nr <<= 1; - if (pack_x_pitch > 4) { - pack_x_pitch >>= 1; - } - - if (pack_y_pitch > 2) { - pack_y_pitch >>= 1; - pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h); - } - } - - } - /* The 965's sampler lays cachelines out according to how accesses - * in the texture surfaces run, so they may be "vertical" through - * memory. As a result, the docs say in Surface Padding Requirements: - * Sampling Engine Surfaces that two extra rows of padding are required. - */ - if (mt->target == GL_TEXTURE_CUBE_MAP) - mt->total_height += 2; + case GL_TEXTURE_3D: + brw_miptree_layout_texture_3d(intel, mt); break; - } case GL_TEXTURE_2D_ARRAY: case GL_TEXTURE_1D_ARRAY: -- 2.30.2