From bc5b660df78ace16d279b7bd8ae59bdaa42c4599 Mon Sep 17 00:00:00 2001 From: colepoirier Date: Thu, 4 Jun 2020 15:37:19 -0700 Subject: [PATCH] Use a_i and b_i convenience variables instead of a and b registers in fu/trap/main_stage --- src/soc/fu/trap/main_stage.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 5d29838f..a241a7d4 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -156,8 +156,7 @@ class TrapMainStage(PipeModBase): with m.Else(): for stt, end in [(1,12), (13, 60), (61, 64)]: - # TODO a_i not a - comb += msr_o.data[stt:end].eq(a[stt:end]) + comb += msr_o.data[stt:end].eq(a_i[stt:end]) with m.If(a[MSR_PR]): msr_o[MSR_EE].eq(1) msr_o[MSR_IR].eq(1) @@ -191,12 +190,10 @@ class TrapMainStage(PipeModBase): ctrl_tmp.msr(MSR_DR) <= '1'; end if; """ - # TODO a_i not a, from the convenience variables - comb += nia_o.data.eq(br_ext(a[63:1] & 0)) + comb += nia_o.data.eq(br_ext(a_i[2:])) comb += nia_o.ok.eq(1) for stt, end in [(0,16), (22, 27), (31, 64)]: - # TODO b_i not a, look above, the VHDL uses b_in - comb += msr_o.data[stt:end].eq(a[stt:end]) + comb += msr_o.data[stt:end].eq(b_i[stt:end]) with m.If(a[MSR_PR]): msr_o[MSR_EE].eq(1) msr_o[MSR_IR].eq(1) -- 2.30.2