From bc60631d6842829fdc48af025372e4913e09cf17 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 12 Dec 2018 10:12:35 +0000 Subject: [PATCH] genlib.cdc.MultiReg: pull in from Migen. --- examples/cdc.py | 10 ++++++++++ nmigen/genlib/__init__.py | 0 nmigen/genlib/cdc.py | 22 ++++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 examples/cdc.py create mode 100644 nmigen/genlib/__init__.py create mode 100644 nmigen/genlib/cdc.py diff --git a/examples/cdc.py b/examples/cdc.py new file mode 100644 index 0000000..caaf679 --- /dev/null +++ b/examples/cdc.py @@ -0,0 +1,10 @@ +from nmigen.fhdl import * +from nmigen.back import rtlil, verilog +from nmigen.genlib.cdc import * + + +sys = ClockDomain() +i, o = Signal(name="i"), Signal(name="o") +frag = MultiReg(i, o).get_fragment(platform=None) +# print(rtlil.convert(frag, ports=[i, o], clock_domains={"sys": sys})) +print(verilog.convert(frag, ports=[i, o], clock_domains={"sys": sys})) diff --git a/nmigen/genlib/__init__.py b/nmigen/genlib/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/nmigen/genlib/cdc.py b/nmigen/genlib/cdc.py new file mode 100644 index 0000000..c7d77e7 --- /dev/null +++ b/nmigen/genlib/cdc.py @@ -0,0 +1,22 @@ +from ..fhdl import * + + +__all__ = ["MultiReg"] + + +class MultiReg(Module): + def __init__(self, i, o, odomain="sys", n=2, reset=0): + self.i = i + self.o = o + self.odomain = odomain + + self.regs = [Signal(self.i.bits_sign(), name="cdc{}".format(i), + reset=reset, reset_less=True)#, attrs=("no_retiming",)) + for i in range(n)] + + def get_fragment(self, platform): + f = Module() + for i, o in zip((self.i, *self.regs), self.regs): + f.sync[self.odomain] += o.eq(i) + f.comb += self.o.eq(self.regs[-1]) + return f.lower(platform) -- 2.30.2